參數(shù)資料
型號： MSC8144VT800A
廠商： Freescale Semiconductor
文件頁數(shù)： 29/80頁
文件大?。?/td> 0K
描述： IC DSP QUAD 800MHZ 783FCBGA
標準包裝： 1
系列： StarCore
類型： SC3400 內(nèi)核
接口： 以太網(wǎng)，I²C，SPI，TDM，UART，UTOPIA
時鐘速率： 800MHz
非易失內(nèi)存： 外部
芯片上RAM： 10.5MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.00V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應商設備封裝： 783-FCPBGA（29x29）
包裝： 托盤
Electrical Characteristics
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
35
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.
2.6.1
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.2
describes the clocking characteristics. Section 2.6.3 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8144 device:
PORESET and TRST must be asserted externally for the duration of the power-up sequence using the VDDIO (3.3 V)
supply. See Table 19 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion.
During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp.
Note:
For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the
VDDM3IO (2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information.
CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation
(see Figure 6). 32 cycles should be accounted only after VDDIO reaches its nominal value.
CLKIN and PCI_CLK_IN should either be stable low during the power-up of VDDIO supply and start their swings after
power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows
during power-up.
Figure 6 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to toggle with the raise of VDDIO supply.
2.6.2
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 16 shows the maximum frequency values for
CLKIN and PCI_CLK_IN. The user must ensure that maximum frequency values are not exceeded.
Figure 6. Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO
Table 16. Clock Frequencies
Characteristic
Symbol
Min
Max
Unit
CLKIN frequency
FCLKIN
33
133
MHz
PCI_CLK_IN frequency
FPCI_CLK_IN
33
133
MHz
CLKIN duty cycle
DCLKIN
40
60
%
PCI_CLK_IN duty cycle
DPCI_CLK_IN
40
60
%
Vo
lt
a
g
e
Time
3.3 V
VDDIO Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied
PORESET
1
VDDIO applied
1.0 V
VDDIO = Nominal
VDD = Nominal
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相關代理商/技術參數(shù)
參數(shù)描述
MSC8144VT800B 制造商:Freescale Semiconductor 功能描述:DSP 32-Bit 800MHz 800MIPS 783-Pin FCBGA 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC81450M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS AVIONICS APPLICATIONS
MSC8151 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Single-Core Digital Signal Processor
MSC8151SAG1000B 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Bulk 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Trays 制造商:Freescale Semiconductor 功能描述:IC DSP 1X 1GHZ SC3850 783FCBGA
MSC8151SVT1000B 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Darwin RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
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