參數(shù)資料
型號(hào)： MSC8101VT1500F
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 54/104頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 250MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 75°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤
AC Timings
MSC8101 Technical Data, Rev. 19
Freescale Semiconductor
2-13
2.6.5
System Bus Access Timing
2.6.5.1 Core Data Transfers
Generally, all MSC8101 bus and system output signals are driven from the rising edge of the reference clock
(REFCLK), which is DLLIN. Memory controller signals, however, trigger on four points within a DLLIN cycle.
Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of DLLIN (and
T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-15 shows.
Figure 2-9 is a graphical representation of Table 2-15.
Note:
The UPM machine and GPCM machine outputs change on the internal tick determined by the memory
controller programming; the AC specifications are relative to the internal tick. SDRAM machine outputs
change only on the DLLIN rising edge.
Table 2-15.
Tick Spacing for Memory Controller Signals
PLL Clock Ratio
Tick Spacing (T1 Occurs at the Rising Edge of DLLIN)
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 DLLIN
1/2 DLLIN
3/4 DLLIN
1:2.5
3/10 DLLIN
1/2 DLLIN
8/10 DLLIN
1:3.5
4/14 DLLIN
1/2 DLLIN
11/14 DLLIN
Figure 2-9.
Internal Tick Spacing for Memory Controller Signals
Table 2-16.
AC Timing for SIU Inputs
No.
Characteristic
Value2
Units
10
Hold time for all signals after the 50% level of the DLLIN rising edge
0.5
ns
11a
ABB/AACK set-up time before the 50% level of the DLLIN rising edge
3.5
ns
11b
DBG/DBB/BR/TC set-up time before the 50% level of the DLLIN rising edge
5.0
ns
11c
ARTRY set-up time before the 50% level of the DLLIN rising edge
4.0
ns
11d
TA set-up time before the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
3.5
4.0
ns
11e
TEA set-up time before the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
4.0
3.0
ns
11f
PSDVAL set-up time before the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
3.5
ns
DLLIN
T1
T2
T3
T4
DLLIN
T1
T2
T3
T4
for 1:2.5
for 1:3.5
DLLIN
T1
T2
T3
T4
for 1:2, 1:3, 1:4, 1:5, 1:6
相關(guān)PDF資料
PDF描述
MSC8103M1200F DSP 16BIT 300MHZ CPM 332-FCPBGA
MSC8103VT1200F IC DSP 16BIT 300MHZ 332-FCPBGA
MSC8112TVT2400V DSP DUAL CORE 431-FCPBGA
MSC8113TVT4800V DSP TRI-CORE 431-FCPBGA
MSC8122MP8000 DSP 16BIT 500MHZ MULTI 431FCPBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8102 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC81020 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS GENERAL PURPOSE AMPLIFIER APPLICATIONS
MSC8102M4000 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC8102M4400 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC8102RM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*