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| 型號： | MPC823 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Communication Processor Module |
| 中文描述： | 通信處理器模塊 |
| 文件頁數(shù)： | 71/74頁 |
| 文件大小： | 234K |
| 代理商： | MPC823 |
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Communication Processor Module
MOTOROLA
MPC823 REFERENCE MANUAL
16-449
S
C
1
P
16.12.4.3 SPI EVENT REGISTER.
The 8-bit memory-mapped SPI event (SPIE) register is
used to generate interrupts and report events recognized by the serial peripheral interface.
When an event is recognized, the serial peripheral interface sets the corresponding bit in
this register. Interrupts generated by this register can be masked in the SPIM register. A bit
is cleared by writing a 1 (writing a zero has no effect) and more than one bit can be cleared
at a time. However, all unmasked bits must be cleared before the communication processor
module clears the internal interrupt request. This register is cleared by reset and can be read
at any time.
Bits 0–1 and 4—Reserved
These bits are reserved and must be set to 0.
MME—Multi-Master Error
This bit indicates that the serial peripheral interface has discovered that the SPISEL pin was
asserted externally while the serial peripheral interface was in master mode.
TXE—TX Error
This bit indicates that an error has occurred during transmission.
BSY—Busy Condition
This bit indicates that received data has been discarded due to a lack of buffers. This bit is
set after the first character is received for which there is no receive buffer.
TXB—TX Buffer
This bit indicates that a buffer has been transmitted. It is set once the transmit data of the
last character in the buffer is written to the transmit FIFO. You must wait two character times
to be sure that the data is completely sent over the transmit pin.
RXB—RX Buffer
This bit indicates that a buffer has been received. It set after the last character is written to
the receive buffer and the RX buffer descriptor is closed.
SPIE
BIT
0
1
2
3
4
5
6
7
FIELD
RESERVED
MME
TXE
RES
BSY
TXB
RXB
RESET
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xAA6
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