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| 型號(hào)： | MPC823 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Communication Processor Module |
| 中文描述： | 通信處理器模塊 |
| 文件頁數(shù)： | 42/74頁 |
| 文件大小： | 234K |
| 代理商： | MPC823 |
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Communication Processor Module
16-420
MPC823 REFERENCE MANUAL
MOTOROLA
S
C
1
P
16.11.7.13 SMCx TRANSPARENT MASK REGISTER.
When a serial management
controller is in transparent mode, the 8-bit read/write SMCx mask register is referred to as
the SMCx transparent mask (SMCM–Transparent) register. It has the same bit format as the
SMCE–Transparent register. If a bit in this register is a 1, the corresponding interrupt in the
SMCE–Transparent register is enabled. If the bit is zero, the corresponding interrupt is
masked.
16.11.7.14 SMCx TRANSPARENT NMSI PROGRAMMING EXAMPLE.
The following is
an example initialization sequence for an SMC1 transparent channel over its own set of pins.
The transmit and receive clocks are provided by the CLK3 pin and the SMSYN1 pin is used
to obtain synchronization.
1. Configure the port B pins to enable the SMTXD1, SMRXD1, and SMSYN1 pins. Write
PBPAR bits 25, 24, and 23 with ones and then PBDIR and PBODR bits 25, 24, and 23
with zeros.
2. Configure the port A pins to enable CLK3. Write PAPAR bit 5 with a one and PADIR
bit 5 with a zero. The other functions of this pin are the timers or the time-slot assigner.
These alternate functions cannot be used on this pin.
3. Connect the CLK3 clock to SMC1 using the serial interface. Write the SMC1 bit in the
SIMODE register with a 0 and the SMC1CS field in the SIMODE register with 110.
4. Write RBASE and TBASE in the SMCx parameter RAM to point to the RX buffer
descriptor and TX buffer descriptor in the dual-port RAM. Assuming one RX buffer
descriptor at the beginning of the dual-port RAM and one TX buffer descriptor following
that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008.
5. Program the CPCR to execute the
INIT RX AND TX PARAMS
command. Write
0x0091 to the CPCR.
6. Write 0x0001 to the SDCR to initialize the SDMA configuration register.
7. Write 0x18 to RFCR and TFCR for normal operation.
8. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16
bytes, so MRBLR = 0x0010.
9. Initialize the RX buffer descriptor and assume the RX data buffer is at 0x00001000 in
main memory. Write 0xB000 to RX_BD_Status, 0x0000 to RX_BD_Length (optional),
and 0x00001000 to RX_BD_Pointer.
SMCM–TRANSPARENT
BIT
0
1
2
3
4
5
6
7
FIELD
RESERVED
TXE
RES
BSY
TX
RX
RESET
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xA8A (SMC1), 0xA9A (SMC2)
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