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| 型號： | MPC823 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Communication Processor Module |
| 中文描述： | 通信處理器模塊 |
| 文件頁數(shù)： | 49/74頁 |
| 文件大小： | 234K |
| 代理商： | MPC823 |
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Communication Processor Module
MOTOROLA
MPC823 REFERENCE MANUAL
16-427
S
C
1
P
C/I_TXBD—The SMCx circuit interface channel transmit (TX) buffer descriptor is used
by the communication processor module to report information about the circuit interface
channel transmit byte.
R—Ready
0 =
The communication processor module clears this bit after transmission to
indicate that the buffer descriptor is now available to the core.
The core sets this bit to indicate that the data associated with this buffer
descriptor is ready for transmission.
Bits 1–7 and 14–15—Reserved
These bits are reserved and must be set to 0.
1 =
C/I DATA—Command/Indication Data Bits
This field represents a 4-bit data field for circuit interface channel 0 and a 6-bit data field
for circuit interface channel 1. It contains the data to be transmitted onto the circuit
interface channel. For circuit interface channel 0, bits 10-13 contain the 4-bit data field
and bits 8 and 9 are always written with zeros. For circuit interface channel 1, bits 8-13
contain the 6-bit data field.
TEMP1–4—These bits are used internally by the RISC microcontroller.
16.11.8.3 SMCx GCI COMMANDS.
The following commands are issued to the CPM
command register.
INIT TX AND RX PARAMS—
This command initializes the transmit and receive
parameters in the parameter RAM to their reset state and it is especially useful when
switching protocols on a given serial channel.
TRANSMIT ABORT REQUEST
—This receiver command can be issued when the
MPC823 implements the monitor channel protocol. When it is issued, the MPC823
sends an abort request on the A bit.
TIMEOUT
—This transmitter command can be issued when the MPC823 implements
the monitor channel protocol and it is usually issued because the device is not
responding or A bit errors are detected. The MPC823 sends an abort request on the E
bit at the time this command is issued.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OFFSET + 0
R
RESERVED
C/I DATA
RESERVED
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