參數(shù)資料
型號(hào)： MPC5553MVR132
廠商： Freescale Semiconductor
文件頁數(shù)： 64/68頁
文件大?。?/td> 0K
描述： MCU 1.5MB FLASH 132MHZ 416-PBGA
標(biāo)準(zhǔn)包裝： 200
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 132MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 220
程序存儲(chǔ)器容量： 1.5MB（1.5M x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 40x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 416-BBGA
包裝： 托盤
Revision History for the MPC5553 Data Sheet
MPC5553 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
67
Deleted (MTS) from the heading, table, and footnotes.
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Footnote 1: Deleted ‘FSYS = 132 MHz’, ‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and
‘a(chǎn)nd CL = 200 pF with SRC = 0b11.’
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Figure 17 (eMIOS Timing) Added eMIOS Timing figure.
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;
114 MHz parts allow for 112 MHz system clock + 2% FM, and 132 MHz parts allow for 128 MHz system clock +
2% FM.
Spec 1: SCK cycle time; Changed 80 MHz = 24.4, and 112 MHz = 17.5.
Footnote 1: Changed to read: ‘All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type
M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.’ Deleted
‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6 V.
Table 27 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics:
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’
Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’
Spec 1: FCK frequency -- removed.
Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 that is now
footnote 2 to Spec 2.
Footnote 1, deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6V.’
Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when. . . .
Removed the ‘M’ in the diagram labels that refer to the specification numbers.
Figure 37 (MPC5553 208-Pin Package)MPC5553 208 Package: Deleted the version number and date.
Figure 38 (MPC5553 324 TEPBGA Package)MPC5553 324 Package: Deleted the version number and date.
Package: Deleted the version number and date.
Table 33. Table and Figure Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
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