參數(shù)資料
型號(hào)： MK2069-04GITR
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁(yè)數(shù)： 9/19頁(yè)
文件大?。?/td> 449K
代理商： MK2069-04GITR
VCXO-Based Universal Clock Translator
MDS 2069-04 G
17
Revision 090905
Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 297 -1 201 l
MK2069-04
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85
° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Crystal Frequency Range
(Note 1)
fXTAL
Using recommended
crystal
13.5
27
MHz
VCXO Crystal Pull Range
fXP
Using recommended
crystal
±115
±150
ppm
VCXO Crystal Free-Run
Frequency (Note 2)
fXF
Input reference = 0 Hz
-300
-150
ppm
Input Clock Frequency when
RPV Divider = 8 (Note 3)
fI
0.008
170
MHz
Input Clock Frequency when
RPV Divider = 1 (Note 3, 4)
fI
0.002
160
MHz
Input Clock Pulse Width
tID
Positive or Negative
Pulse
10
nsec
VCXO PLL Phase Detector
Frequency (Note 3)
fPD
0.001
27
MHz
VCXO PLL Phase Detector Jitter
Tolerance
tJT
1 UI = phase detector
period
0.4
UI
Translator PLL VCO Frequency
fV
40
320
MHz
Timing Jitter, Filtered
500 Hz-1.3 MHz (OC-3)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
95
ps
Timing Jitter, Filtered
65 kHz-5 MHz (OC-3)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
85
ps
Timing Jitter, Filtered
1 kHz-5 MHz (OC-12)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
105
ps
Timing Jitter, Filtered
250 kHz-5 MHz (OC-12)
tOJf
Derived from phase
noise characteristics,
peak-to-peak 6 sigma
80
ps
Output Duty Cycle (% high time),
VCLK when SV Divider = 1
tOD
Measured at VDD/2,
CL=15 pF
40
50
60
%
Output Duty Cycle (% high time),
VCLK when SV Divider > 1,
TCLK
tOD
Measured at VDD/2,
CL=15 pF
44
50
65
%
Output High Time, RCLK
(Note 5)
tOH
Measured at VDD/2,
CL=15 pF
0.5
VCLK
Period
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