參數(shù)資料
型號： MK2069-04GITR
元件分類： 時鐘產(chǎn)生/分配
英文描述： 160 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, TSSOP-56
文件頁數(shù)： 12/19頁
文件大小： 449K
代理商： MK2069-04GITR
VCXO-Based Universal Clock Translator
MDS 2069-04 G
2
Revision 090905
Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 297 -1 201 l
MK2069-04
Pin Assignment
Input Selection Tables
VCXO PLL Reference Pre-Divider Selection
Table
VCXO PLL Reference Divider Selection Table
VCXO PLL Feedback Divider Selection
VCXO PLL Scaling Divider Selection Table
Translator PLL Feedback Divider Selection
Translator PLL Scaling Divider Selection Table
21
FV 0
22
FV 1
23
FV 2
24
FV 3
1
RV 5
2
RV 6
3
RV 7
4
RV 8
5
FT 0
6
FT 1
7
FT 2
8
RV 9
9
RV 1 0
10
RV 1 1
11
ST
12
VD D T
13
GN D T
14
X1
15
V DDV
16
X2
17
G NDV
18
LF R
19
LF
20
ISET
25
FV 4
26
FV 5
27
FV 6
28
FV 7
36
35
34
33
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
32
31
30
29
CL R
IC L K
RV 1
RV 0
RP V
SV1
SV0
RV 4
RV 3
RV 2
OE L
OE T
OE V
OE R
VD D
LD
TC L K
VD D P
VC L K
GN D P
RCL K
LD R
GN D
LD C
FV 1 1
FV 1 0
FV 9
FV 8
M
K
2069-
0
4
RPV RPV Pre-Divider Ratio
0
1
8
RV11:0
RV Divider
Ratio
Notes
0...00
2
RV Divide Value
= Address + 2
0...01
3
:
1...11
4097
FV11:0 FV Divider Ratio
Notes
0...00
2
For FV addresses 0 to 4094,
FV Divide Value
= Address + 2
0...01
3
:
1...10
4096
1...11
1
SV1
SV0
SV Divider Ratio
0
12
0
1
2
1
0
16
1
FT2
FT1
FT0
FT Divider Ratio
0
4
0
1
6
0
1
0
8
0
1
10
1
0
12
1
0
1
14
1
0
16
1
2
ST
ST Divider Ratio
0
2
1
16
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