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參數(shù)資料
| 型號： | MK2069-04GITR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 449K |
| 代理商： | MK2069-04GITR |
VCXO-Based Universal Clock Translator
MDS 2069-04 G
4
Revision 090905
Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 297 -1 201 l
MK2069-04
Functional Description
The MK2069-04 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock. It contains
two cascaded PLL’s with user selectable divider ratios.
The first PLL is VCXO-based and uses an external
pullable crystal as part of the normal “VCO” (voltage
controlled oscillator) function of the PLL. The use of a
VCXO assures a low phase noise clock source even
when a low PLL loop bandwidth is implemented. A low
loop bandwidth is needed when the input reference
frequency at the phase detector is low, or when jitter
attenuation of the input reference is desired.
The second PLL is used to translate or multiply the
frequency of the VCXO PLL which has a maximum
output frequency of 27 MHz. This second PLL, or
Translator PLL, uses an on-chip VCO circuit that can
provide an output clock up to 160 MHz. The Translator
PLL uses a high loop bandwidth (typically greater than
1 MHz) to assure stability of the clock output generated
by the VCO. It requires a stable, high frequency input
reference which is provided by the VCXO.
The divide values of the divider blocks within both PLLs
are set by device pin configuration. This enables the
system designer to define the following:
Input clock frequency
VCXO crystal frequency
VCLK output frequency
RCLK output frequency, which is also the phase
detector frequency of the VCXO PLL.
TCLK output frequency
Any unused clock or logic outputs can be tri-stated to
reduce interference (jitter, phase noise) on other clock
outputs. Outputs can also be tri-stated for system
testing purposes.
External components are used to configure the VCXO
PLL loop response. This serves to maximize loop
stability and to achieve the desired input clock jitter
attenuation characteristics.
42
VCLK
Output
Clock output from VCXO PLL
43
VDDP
Power
Power Supply for output drivers (VCLK, TCLK, RCLK, LD, LDR).
44
TCLK
Output
Clock output from Translator PLL
45
LD
Output
Lock detector output.
46
VDD
Power
Power Supply connection for internal digital circuitry.
47
OER
Input
Output enable for RCLK. RCLK is tri-stated when low, internal pull-up.
48
OEV
Input
Output enable for VCLK. VCLK is tri-stated when low, internal pull-up.
49
OET
Input
Output enable for TCLK. TCLK is tri-stated when low, internal pull-up.
50
OEL
Input
Output enable for LD. LD is tri-stated when low, internal pull-up.
51
RV2
Input
Reference Divider bit 2 input, VCXO PLL, internal pull-up.
52
RV3
Input
Reference Divider bit 3 input, VCXO PLL, internal pull-up.
53
RV4
Input
Reference Divider bit 4 input, VCXO PLL, internal pull-up.
54
SV0
Input
Scaler Divider bit 0 input, VCXO PLL, internal pull-up.
55
SV1
Input
Scaler Divider bit 1 input, VCXO PLL, internal pull-up.
56
RPV
Input
RPV divider, VCXO PLL, internal pull-up.
Pin
Number
Pin
Name
Pin
Type
Pin Description
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