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參數(shù)資料
| 型號(hào)： | MK2069-04GITR |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 449K |
| 代理商： | MK2069-04GITR |
VCXO-Based Universal Clock Translator
MDS 2069-04 G
3
Revision 090905
Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 297 -1 201 l
MK2069-04
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
RV5
Input
Reference Divider bit 5 input, VCXO PLL, internal pull-up.
2
RV6
Input
Reference Divider bit 6 input, VCXO PLL, internal pull-up.
3
RV7
Input
Reference Divider bit 7 input, VCXO PLL, internal pull-up.
4
RV8
Input
Reference Divider bit 8 input, VCXO PLL, internal pull-up.
5
FT0
Input
Feedback Divider bit 0 input, Translator PLL, internal pull-up.
6
FT1
Input
Feedback Divider bit 1 input, Translator PLL, internal pull-up.
7
FT2
Input
Feedback Divider bit 2 input, Translator PLL, internal pull-up.
8
RV9
Input
Reference Divider bit 9, VCXO PLL, internal pull-up.
9
RV10
Input
Reference Divider bit 10, VCXO PLL, internal pull-up.
10
RV11
Input
Reference Divider bit 11, VCXO PLL, internal pull-up.
11
ST
Input
Scaling Divider selection bit, Translator PLL, internal pull-up.
12
VDDT
Power
Power Supply connection for translator PLL.
13
GNDT
Ground
Ground connection for translator PLL.
14
X1
—
Crystal oscillator input. Connect this pin to the external quartz crystal.
15
VDDV
Power
Power Supply connection for VCXO PLL.
16
X2
—
Crystal oscillator output. Connect this pin to the external quartz crystal.
17
GNDV
Ground
Ground connection for VCXO PLL.
18
LFR
—
Loop filter connection, reference node. Refer to loop filter circuit on page 6.
19
LF
—
Loop filter connection, active node. Refer to loop filter circuit on page 6.
20
ISET
—
Charge pump current setting pin. Refer to loop filter circuit on page 6.
21
FV0
Input
Feedback Divider bit 0 input, VCXO PLL, internal pull-up.
22
FV1
Input
Feedback Divider bit 1input, VCXO PLL, internal pull-up.
23
FV2
Input
Feedback Divider bit 2 input, VCXO PLL, internal pull-up.
24
FV3
Input
Feedback Divider bit 3 input, VCXO PLL, internal pull-up.
25
FV4
Input
Feedback Divider bit 4 input, VCXO PLL, internal pull-up.
26
FV5
Input
Feedback Divider bit 5 input, VCXO PLL, internal pull-up.
27
FV6
Input
Feedback Divider bit 6 input, VCXO PLL, internal pull-up.
28
FV7
Input
Feedback Divider bit 7 input, VCXO PLL, internal pull-up.
29
FV8
Input
Feedback Divider bit 8 input, VCXO PLL, internal pull-up.
30
FV9
Input
Feedback Divider bit 9 input, VCXO PLL, internal pull-up.
31
FV10
Input
Feedback Divider bit 10 input, VCXO PLL, internal pull-up.
32
FV11
Input
Feedback Divider bit 11 input, VCXO PLL, internal pull-up.
33
RV0
Input
Reference Divider bit 0, VCXO PLL, internal pull-up.
34
RV1
Input
Reference Divider bit 1, VCXO PLL, internal pull-up.
35
ICLK
Input
Reference clock input, 5 V tolerant input
36
CLR
Input
Clear input, allows VCXO to free-run when low, internal pull-up.
37
LDC
—
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
38
GND
Ground
Ground connection for internal digital circuitry.
39
LDR
Power
Lock detector threshold setting circuit connection. Refer to circuit on page 10.
40
RCLK
—
VCXO PLL phase detector Reference Clock output.
41
GNDP
Ground
Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
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