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參數(shù)資料
| 型號： | MK2069-04GITR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 18/19頁 |
| 文件大小： | 449K |
| 代理商： | MK2069-04GITR |
VCXO-Based Universal Clock Translator
MDS 2069-04 G
8
Revision 090905
Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 297 -1 201 l
MK2069-04
VCXO Gain (KO) vs. XTAL Frequency
Setting the RPV, RV, FV and SV Divider
Values in the VCXO PLL
As shown in the loop bandwidth and damping factor
equations on page 6, or by using the filter response
software available from ICS, increasing FV or SV
decreases both bandwidth and damping factor. Many
applications require that SV = 1. In these cases, one
way to decrease loop bandwidth is to increase the
value of FV, which is accompanied by an increase in
the value of RPV and/or RV to maintain the same PLL
frequency multiplication ratio.
However, the phase detector frequency, FPD, also
needs to be considered. FPD is equal to the input
frequency divided by the value of the RPV x RV. FPD
should be typically at least 20x the loop bandwidth to
prevent loop modulation (phase noise) by the phase
detector frequency. The phase detector jitter tolerance
limit (use 0.4UI) and input phase noise frequency
aliasing should be considerations as well.
Example Loop Filter Component Value
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy
wander transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a
system synchronizer such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3
compliance. A 155.52 MHz TCLK output generated with the VCXO PLL configuration will be OC-3 and OC-12
timing jitter compliant.
2) This is a reduced cost and size variant of the above filter, due to the decreased size of CS. It is useful when
GR-1244-CORE compliance is not needed.
3) This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration
is GR-1244-CORE compliant when used following a system synchronizer.
4) Lowering the phase detector frequency, by increasing the value of the RPV and/or RV dividers and the FV
divider, will lower the loop bandwidth and/or decrease the size of CS for the same damping factor.
10
20
1 5
25
30
2000
3000
4000
5000
6000
1000
C rystal F requ e ncy, M H z
VC
XO
G
a
in
(
K
O
),
H
z
p
e
r
V
o
lt
Phase
Detector
Frequency
Xtal
Freq
(MHz)
SV
Div
VCLK
(MHz)
FV
Div
RSET
RS
CS
CP
Loop
BW
(-3dB)
Loop
Damp.
Passband
Peaking
Note
8 kHz
19.44
1
19.44
2430 1 M
560 k 1 F
4.7 nF
22 Hz
4.0
0.15dB at 1Hz
1
8 kHz
19.44
1
19.44
2430 1 M
560 k 0.1 F 4.7 nF 27 Hz
1.4
1.2dB at 6Hz
2
8 kHz
22.368
1
22.368 2796 1 M
680 k 1 F
4.7 nF
20 Hz
4.5
0.12dB at 1Hz
3
19.44 MHz
19.44
1
19.44
128
1 M
27 k
1
F
47 nF
25 Hz
0.85
1.8dB at 8Hz
4
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