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參數(shù)資料
| 型號： | MH28D72KLG-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 37/39頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MH28D72KLG-10 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
37
EEPROM Components A.C. and D.C. Characteristics
Limits
Typ.
Min.
2.2
Max.
5.5
V
V
V
V
0
Vcc+0.5
0
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
-1
V
IL
V
OL
Symbol
Parameter
Units
Vccx0.3
Vccx0.7
V
Output Low Voltage
0.4
EEPROM A.C.Timing Parameters
(Ta=0 to 70
°C
)
Limits
Min.
Max.
100
KHz
ns
us
200
3.5
4.7
SCL Clock Frequency
Noise Supression Time Constant at SCL, SDA inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New
Transmission Can Start
fSCL
TI
TAA
us
4.7
TBUF
Symbol
Parameter
Units
4.0
us
Start Condition Hold Time
THD:STA
4.0
us
Clock Low Time
TLOW
4.7
us
us
Clock High Time
THIGH
0
Start Condition Setup Time
TSU:STA
250
us
ns
Data In Hold Time
Data In Setup Time
THD:DAT
TSU:DAT
us
SDA and SCL Rise Time
TR
ns
SDA and SCL Fall Time
TF
us
Stop Condition Setup Time
TSU:STO
4.0
ns
Data Out Hold Time
TDH
100
ms
Write Cycle Time
TWR
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
0
300
1
10
SCL
SDA
IN
T
SU:STA
T
HD:STA
T
F
T
LOW
T
HIGH
T
R
T
HD:DAT
T
SU:DAT
T
SU:STO
T
BUF
SDA
OUT
T
AA
T
DH
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