參數(shù)資料
型號(hào)： MH28D72KLG-10
廠商： Mitsubishi Electric Corporation
英文描述： 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
中文描述： 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊
文件頁數(shù)： 23/39頁
文件大?。?/td> 337K
代理商： MH28D72KLG-10
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
23
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the
Burst Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data
is defined by the Burst Type. A READ command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous output data by interleaving the
multiple banks. When A10 is high at a READ command, the auto-precharge(READA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at BL/2(Discrete, In case of module, BL/2+1) after
READA. The next ACT command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2(Discrete level))
Module input and output timing.
/CLK
CLK
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
READ
Y
0
10
ACT
Xb
Xb
10
PRE
0
00
tRCD
Module /CAS latency(Discrete CL + 1)
Burst Length
DQS
Qa0
Qa1 Qa2 Qa3
Qa4 Qa5 Qa6 Qa7 Qb0 Qb1
Qb2 Qb3 Qb4 Qb5 Qb7
相關(guān)PDF資料
PDF描述
MH28D72KLG-75 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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