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參數(shù)資料
| 型號： | MH28D72KLG-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 31/39頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MH28D72KLG-10 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
31
[Initialize and Mode Register sets]
Command
/CLK
CLK
EMRS
PRE
NOP
MRS
PRE
AR
AR
MRS
ACT
Code
Code
Xa
Code
Xa
1 0
Xa
A0-9,11,12
A10
Code
1
BA0,1
DQS
DQ
1
0 0
0 0
Code
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The
refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbits memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be
supplied to the device before tRFC from the REFA command.
Auto-Refresh
/RAS
CKE
/CS
/CAS
/WE
A0-12
BA0,1
NOP or DESELECT
tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
/CLK
CLK
Code
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| MH28D72KLG-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
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