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參數(shù)資料
| 型號： | MH28D72KLG-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 9663676416位（134217728 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 22/39頁 |
| 文件大?。?/td> | 337K |
| 代理商： | MH28D72KLG-10 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0412-0.1
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
22
A precharge command can be issued at BL/2(Discrete) from a read command without data loss.
Precharge all
Bank Activation and Precharge All (BL=8, CL=2 (Discrete level))
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
tRAS
tRP
tRCmin
2 ACT command / tRCmin
DQS
Qa0
BL/2
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command
with the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum
activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands
are allowed within tRC,although the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same
time. After tRP from the precharge, an ACT command to the same bank can be issued.
Qa1
Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
/CLK
CLK
Module input and output timing.
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| MH28D72KLG-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
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