參數(shù)資料
型號： MFRC50001T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Highly integrated ISO-IEC 14443 A reader IC
封裝： MFRC50001T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 15, 2005,;
文件頁數(shù)： 21/110頁
文件大?。?/td> 841K
代理商： MFRC50001T
MFRC500_33
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.3 — 15 March 2010
048033
21 of 110
NXP Semiconductors
MFRC500
Highly Integrated ISO/IEC 14443 A Reader IC
transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic 1
transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd = logic 1
bit TStartNow is set to logic 1 by the microprocessor
Remark:
Every start event reloads the timer from the TimerReload register which
re-triggers the timer unit.
The timer can be configured to stop on one of the following events:
receipt of the first valid bit from the card (RxBegin event) with bit
TStopRxBegin = logic 1
receipt of the last bit from the card (RxEnd event) with bit TStopRxEnd = logic 1
the counter module has decremented down to zero and bit TAutoRestart = logic 0
bit TStopNow is set to logic 1 by the microprocessor.
Loading a new value, e.g. zero, into the TimerReload register or changing the timer unit
while it is counting will not immediately influence the counter. In both cases, this is
because this register only affects the counter content after a start event.
If the counter is stopped when bit TStopNow is set, no TimerIRq is flagged.
9.5.1.3
Timer unit clock and period
The timer unit clock is derived from the 13.56 MHz on-board chip clock using the
programmable divider. Clock selection is made using the TimerClock register
TPreScaler[4:0] bits based on
Equation 3
:
(3)
The values for the TPreScaler[4:0] bits are between 0 and 21 which results in a minimum
periodic time (T
TimerClock
) of between 74 ns and 150 ms.
The time period elapsed since the last start event is calculated using
Equation 4
:
(4)
This results in a minimum time period (t
Timer
) of between 74 ns and 40 s.
9.5.1.4
Timer unit status
The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start
events start the timer at the TReloadValue[7:0] and change the status flag TRunning to
logic 1. Conversely, configured stop events stop the timer and set the TRunning status
flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register
changes on the next timer unit clock cycle.
The TimerValue[7:0] bits can be read directly from the TimerValue register.
f
TimerClock
T
TimerClock
---------------------------
TPreScaler
13.56
--------------------------
MHz
]
[
=
=
t
Timer
----------------------------------------------------------------------------
s
[ ]
f
TimerClock
=
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