LOGIC COMMANDS AND REGISTERS bit is cleared " />
參數(shù)資料
型號： MCZ33781EKR2
廠商： Freescale Semiconductor
文件頁數(shù)： 29/44頁
文件大?。?/td> 0K
描述： IC MASTER DSI 2.02 DIFF 32-SOIC
標準包裝： 1,000
應用： 車載系統(tǒng)
接口： SPI
電源電壓： 4.75 V ~ 5.25 V
封裝/外殼： 32-BSOP（0.295"，7.50mm 寬）裸露焊盤
供應商設備封裝： 32-SOICW 裸露焊盤
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
33781
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
bit is cleared or the ISDD bit is set, or if the high side or low
side pseudo bus thermal limit is exceed. It is necessary to
write a one to the BSWL bit to close the switch again.
EN – Controls Enabling and Disabling of Channel
0 = The Channel is disabled.
1 = The Channel is enabled.
When the channel is disabled, the channel addressed
buffer data bits, the status register bits, and the buffer
pointers are reset. Any DBUS transfer that was in progress is
stopped. If the write is to channel 0, the pseudo bus switches
are also opened and the BSWH and BSWL bits are cleared.
The EN bit is also cleared and the channel disabled if a
thermal shutdown occurs. It is necessary to write a 1 to the
EN bit to turn it back on.
DnPOLY REGISTERS
These read/write registers control the polynomial used for
calculating the CRC that is transmitted/received on the DBUS
channels. There are four of these registers, one for each
DBUS channel. The bit assignments are shown in Figure 30.
Figure 30. Dn Polynomial Register Bit Assignments
Each bit represents a polynomial term in the CRC
equation. Bit 7 represents x7, bit 6 represents x6, and so on.
Both the short and long word command use the same
polynomial. The polynomial bits beyond what is specified in
the CRCLEN[3:0] registers are ignored, and the most
significant term of each polynomial is assumed to be on. So,
for example, to represent a 6-bit CRC with a polynomial of
x6+ x3 + 1, the value in DnPOLY is xx001001. Bits 7 and 6 are
ignored in this case. These registers reset to 00010001 (x4 +
1), which is the default DSI value (bit 4 does not need to be
on for this case, but is included for readability).
A write to the register will abort any current activity on the
bus. Any bit changes will take place on the next DBUS
transaction following the conclusion of the SPI write to the
register.
DnSEED REGISTERS
These read/write registers control the initial value, or seed,
used for calculating the CRC that is transmitted/received on
the DBUS channels. There are four of these registers, one for
each DBUS channel. The bit assignments are shown in
Figure 31. Dn CRC Seed Register Bit Assignments
The bits in these registers form a word that is used as the
seed for the CRC calculations. Both the short and long word
commands use the same seed. The seed bits beyond what is
specified in the CRCLEN[3:0] registers are ignored. So, for
example, to represent a 6-bit CRC with a seed 010101, the
value in DnSEED is xx010101. Bits 7 and 6 are ignored in this
case. These registers reset to 00001010, which is the default
DSI value.
A write to the register will abort any current activity on the
bus. Any bit changes will take place on the next DBUS
transaction following the conclusion of the SPI write to the
register.
DnLENGTH REGISTERS
These read/write registers control the short word lengths
and CRC lengths for data that is transmitted/received on the
DBUS channels. There are four of these registers, one for
each DBUS channel. The bit assignments are shown in
Figure 32. Dn Short Word and CRC Length Register Bit Assignments
A write to the register will abort any current activity on the
bus. Any bit changes will take place on the next DBUS
transaction following the conclusion of the SPI write to the
register.
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
CRCPOLY7 CRCPOLY6 CRCPOLY5 CRCPOLY4 CRCPOLY3 CRCPOLY2 CRCPOLY1 CRCPOLY0
Reset
0
1
0
1
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
CRCSEED7 CRCEED6 CRCEED5 CRCEED4 CRCEED3 CRCEED2 CRCEED1 CRCEED0
Reset
0
1
0
1
0
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
SWLEN3
SWLEN2
SWLEN1
SWLEN0
CRCLEN3
CRCLEN2
CRCLEN1
CRCLEN0
Reset
1
0
1
0
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