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參數(shù)資料
| 型號： | MCZ33781EKR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 13/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MASTER DSI 2.02 DIFF 32-SOIC |
| 標準包裝： | 1,000 |
| 應用： | 車載系統(tǒng) |
| 接口： | SPI |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 封裝/外殼： | 32-BSOP（0.295"，7.50mm 寬）裸露焊盤 |
| 供應商設備封裝： | 32-SOICW 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
20
Freescale Semiconductor
33781
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
PSEUDO BUS SWITCHES
Pseudo Bus Switches are provided on the Channel 0 bus.
They allow one channel to communicate via two external bus
wire sets (D0H/D0L and DPH/DPL). There is a pseudo bus
switch on both the bus high and bus low driver. Upon device
initialize devices on D0H/D0L. After all of these slaves are
initialized, the pseudo bus switches can be closed, allowing
the devices on DPH/DPL to be initialized.
The Pseudo Bus Switches can only be commanded closed
by the BSWH and BSWL bits in the D0EN register. These bits
can also open the switch at any time.
The Pseudo Bus Switches have independent thermal
shutdown protection. Once the thermal shutdown point is
reached, the bus switch is opened (becoming high-
impedance) and the BSWH and/or BSWL bit is cleared in the
channel 0 DEN register. If this occurs, the Pseudo Bus
Switches can only be closed again by setting the BSWH and/
or BSWL bit to a 1 with a write command to the channel 0
DEN register.
SPREAD SPECTRUM
The dominant source of radiated electromagnetic
interference (EMI) from the DBUS bus is due to the regular
periodic frequency of the data bits. At a steady bit rate, the
time period for each bit is the same, which results in a steady
fundamental frequency plus harmonics. This results in
undesired signals appearing at multiples of the frequency
that can be strong enough to interfere with a desired signal.
A significant decrease in radiated EMI can be achieved by
randomly changing the duration of each bit. This can
significantly reduce the amplitude by having the signal spend
a much smaller percentage of time at any specific frequency.
The signal strength of the fundamental and harmonics are
reduced directly by the percentage of time it spends on a
specific frequency.
A circuit to do this is included in this IC, and can perform
the spreading of the signal independently for each channel,
while generating the bit clock timing for the channel. This is
done in the Spread Spectrum (SS) Block Diagram shown in
To implement the channel bit clock a common 64MHz
clock is created from the on board 4MHz oscillator using a
digital PLL. Multiples of this clock period (15.625 nsec) are
used to select the minimum channel bit time. The Spread
Table 7. Receiver Decision Logic
Bus Pin
Conditions
Receiver
High 6 ± 1
mA
Receiver
Low 6 ± 1
mA
Receiver
Sum 12 ±
6mA
High and
Low XOR
(bit/bit)
High and
Sum XOR
(bit/bit)
Low and
Sum XOR
(bit/bit)
ER Bit
SPI0
DnRnxData
SPI1
DnRnxData
Normal
CRC Ok
H*L Ok
N/A
0
Receiver
High
Receiver
Low
H*L Not OK
1
Receiver
High
Receiver
Low
Out of Spec
CRC Ok
Bad CRC
H*L Ok
N/A
0
Receiver
High
Receiver
Low
H*L Not OK
1
Receiver
High
Receiver
Low
Fault
CRC Ok
Bad CRC
CRC Ok
N/A
H*S Ok
N/A
0
Receiver
High
Receiver
Sum1
H*S Not OK
1
Receiver
High
Receiver
Low
Fault L
CRC Ok
Bad CRC
N/A
1
Receiver
High
Receiver
Low
Fault
Bad CRC
CRC OK
N/A
L*S Ok
0
Receiver
Sum0
Receiver
Low
L*S Not OK
1
Receiver
High
Receiver
Low
Fault H
Bad CRC
CRC Ok
Bad CRC
N/A
1
Receiver
High
Receiver
Low
Common
Mode Noise
Bad CRC
CRC Ok
N/A
0
Receiver
Sum0
Receiver
Sum1
Fault
Bad CRC
N/A
1
Receiver
High
Receiver
Low
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