參數(shù)資料
型號： MCZ33781EKR2
廠商： Freescale Semiconductor
文件頁數(shù)： 23/44頁
文件大小： 0K
描述： IC MASTER DSI 2.02 DIFF 32-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 車載系統(tǒng)
接口： SPI
電源電壓： 4.75 V ~ 5.25 V
封裝/外殼： 32-BSOP（0.295"，7.50mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 32-SOICW 裸露焊盤
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
33781
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 33781 Pin Connections
Table 1. 33781 Pin Definitions
A functional description of each Pin can be found in the Functional Pin Descriptions section beginning on page 15.
Pin
Pin Name
Pin Function
Formal Name
Definition
1
RST
Reset
IC Reset
A low level on this pin returns all registers to a known state as indicated
in the sections entitled SPI0 Register and Bit Descriptions and SPI1
2
SCLK0
Input
SPI0 Serial Data Clock Clocks data in from and out to SPI0. MISO0 data changes on the negative
transition of SCLK0. MOSI0 is sampled on the positive edge of SCLK0.
3
MOSI0
Input
SPI0 Master Out Slave
In
SPI data into SPI0. This data input is sampled on the positive edge of
SCLK0
4
MISO0
Output
SPI0 Master In Slave
Out
SPI0 data sent to the MCU by this device. This data output changes on
the negative edge of SCLK0. When CS0 is high, this Pin is high-
impedance.
5
SCLK1
Input
SPI1 Serial Data Clock Clocks data out from SPI1. MISO1 data changes on the negative
transition of SCLK1.
6
MISO1
Output
SPI1 Master In Slave
Out
SPI1 data sent to the MCU by this device. This data output changes on
the negative edge of SCLK1. When CS1 is high, this Pin is high-
impedance.
7
CS0
Input
SPI0 Chip Select
When this signal is high, SPI signals on SPI0 are ignored. Asserting this
pin low starts an SPI0 transaction. The SPI0 transaction is signaled as
completed when this signal returns high.
8
AGND
Ground
Analog Ground
Ground for the analog circuits. This pin is not connected internally to the
other grounds on the chip. It should be connected to a quiet ground on
the board.
9
CS1
Input
SPI1 Chip Select
When this signal is high, SPI signals on SPI1 are ignored. Asserting this
pin low starts an SPI1 transaction. The SPI1 transaction is signaled as
completed when this signal returns high.
10
VSS
Ground
Digital Ground
Digital ground connected internally to the other on-chip grounds. This
ground is connected to circuits that will consume current during IDDQ
testing.
11
VDD
Power
Digital Voltage
Output of the Internal 2.5V regulator for the digital circuits. No external
current draw is allowed from this pin.
1
8
9
10
11
12
13
14
15
16
3
4
5
6
7
2
32
25
24
23
22
21
20
19
18
17
30
29
28
27
26
31
RST
SCLK0
MOSI0
MISO0
SCLK1
MISO1
CS0
AGND
CS1
VSS
VDD
VPP
VCC
CLK
TESTIN
TESTOUT
VSS_IDDQ
GND
D3L
D3H
VSUP2
D2H
D2L
GND
D1L
D1H
VSUP1
D0H
DPH
D0L
DPL
GND
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