- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45313 > MCIMX507CVM8B (FREESCALE SEMICONDUCTOR INC) SPECIALTY MICROPROCESSOR CIRCUIT, PBGA400 PDF資料下載
參數(shù)資料
| 型號： | MCIMX507CVM8B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA400 |
| 封裝： | 17 X 17 MM, 0.5 MM PITCH, ROHS COMPLIANT, PLASTIC, MABGA-400 |
| 文件頁數(shù)： | 30/120頁 |
| 文件大?。?/td> | 1980K |
| 代理商： | MCIMX507CVM8B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
Modules List
i.MX50 Applications Processors for Consumer Products, Rev. 0
Freescale Semiconductor
17
DRAM_OPEN,
DRAM_OPENFB
(416MAPBGA and
400MAPBGA Only)
These pins are the echo gating output and feedback pins used by the DRAM PHY to bound a
window around the DQS transition. For an application using a single DRAM device, these pins
should be routed so that the
trace length (DRAM_OPEN + DRAM_OPENFB) =
trace length (DRAM_SDCLK0 + DRAM_SDQS0).
For an application using two DRAM devices, they should be routed so that the
trace length (DRAM_OPEN + DRAM_OPENFB) =
trace length (AVG(DRAM_SDCLK0+DRAM_SDCLK1) + AVG (DRAM_SDQS0_to_Device0 +
DRAM_SDQS0_to_Device1)).
This connection is required for mDDR, LPDDR2, and DDR2.
DRAM_SDODT0,
DRAM_SDODT1
(416MAPBGA and
400MAPBGA Only)
These pins are the On-die termination outputs from the i.MX50.
For DDR2, these pins should be connected to the DDR2 DRAM ODT pins. For LPDDR2 and
mDDR, these pins should be left floating. Only SDODT0 exists on the 400MAPBGA package.
DRAM_CALIBRATION
This pin is the ZQ calibration used to calibrate DRAM Ron and ODT.
For LPDDR2, this pin should be connected to ground through a 240
Ω 1% resistor. For DDR2
and LPDDR1, this pin should be connected to ground through a 300
Ω 1% resistor.
JTAG_MOD
This input has an internal 100K pull-down. Note that JTAG_MOD is referenced as SJC_MOD in
the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) - both names refer to the
same signal. JTAG_MOD must be externally connected to GND for normal operation. Termination
to GND through an external pull-down resistor (such as 1 k
Ω) is allowed.
JTAG_TCK
This input has an internal 100K pull-down. This pin is in the NVCC_JTAG domain.
JTAG_TDI
This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.
JTAG_TDO
This is a 3-state output with an internal gate keeper enable to prevent a floating condition. An
external pull-up or pull-down resistor on JTAG_TDO is detrimental and should be avoided. This pin
is in the NVCC_JTAG domain.
JTAG_TMS
This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.
JTAG_TRSTB
This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.
NC
These signals are No Connect (NC) and should be floated by the user.
LOW_BATT_GPIO
If the LOW_BATT_GPIO (UART4_TXD) is asserted at power up, the i.MX50 will boot up at a lower
ARM clock frequency to reduce system power. The actual ARM clock frequency used when
LOW_BATT_GPIO is asserted is determined by the BT_LPB_FREQ[1:0] pins (220 MHz to 55.3
MHz). The polarity of the LOW_BATT_GPIO is active high by default, but may be set to active low
by setting the LOW_BATT_GPIO_LEVEL OTP bit.
See the “System Boot” chapter of the Reference Manual for more details.
Note that this is not a dedicated pin: LOW_BATT_GPIO appears on the UART4_TXD pin.
PMIC_STBY_REQ
This output may be driven high when the i.MX50 enters the STOP mode to notify the PMIC to enter
its low power standby state. This output is in the NVCC_SRTC domain.
PMIC_ON_REQ
This output from the i.MX50 can instruct the PMIC to turn on when the i.MX50 only has
NVCC_SRTC power. This may be useful for an alarm application, as it allows the i.MX50 to turn
off all blocks except for the RTC and then power on again at a specified time. This output is in the
NVCC_SRTC domain.
PMIC_RDY
This input may be used by a PMIC to signal to the i.MX50 that the PMIC supply outputs are at
operating levels when resuming from STOP mode. The PMIC_RDY input is pinmuxed on ALT3 of
the I2C3_SCL pin and is in the NVCC_MISC domain.
Table 5. Special Signal Considerations (continued)
Signal Name
Remarks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCIMX512DJM8C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| MCIMX513DJM8C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| MCIMX515CJM6C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| MCIMX512CJM6C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| MCIMX515DJM8C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX508CVK8A | 制造商:Freescale Semiconductor 功能描述:CODEX 13MM W/2025D - Bulk |
| MCIMX508CVK8B | 功能描述:處理器 - 專門應(yīng)用 Codex 1.1 13mm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVK8BR2 | 功能描述:處理器 - 專門應(yīng)用 Codex 1.1 13mm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVM8B | 功能描述:處理器 - 專門應(yīng)用 Codex Rev 1.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVM8BR2 | 功能描述:處理器 - 專門應(yīng)用 Codex Rev 1.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。