參數(shù)資料
型號(hào): MC74LCX00SD
廠商: ON SEMICONDUCTOR
元件分類: 門電路
英文描述: 15 A 12-V Input Bus Termination Power Module for DDR/QDR Memory 10-DIP MODULE -40 to 85
中文描述: LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝: PLASTIC, SSOP-14
文件頁(yè)數(shù): 6/40頁(yè)
文件大小: 350K
代理商: MC74LCX00SD
Definitions of Symbols
MOTOROLA
LCX DATA
BR1339 — REV 3
12
Definitions of Symbols
DC Characteristics
Currents Positive current is defined as conventional current
flow into a device. Negative current is defined as
current flow out of a device.
Voltages All voltages are referenced to the ground pin.
ICC
The current flowing into the VCC supply terminal
when the device is at a quiescent state.
ICCH
The current flowing into the VCC supply terminal
when the outputs are in the HIGH state.
ICCL
The current flowing into the VCC supply terminal
when the outputs are in the LOW state.
ICCZ
The current flowing into the VCC supply terminal
when the outputs are disabled (high impedance).
ICC
Additional ICC due to TTL HIGH levels (VCC – 0.6V)
forced on CMOS inputs.
II
Input Current. The current flowing into or out of an
input when a specified LOW or HIGH voltage is
applied to that input.
IOH
Output HIGH Current. The current flowing out of an
output which is in the HIGH state.
IOL
Output LOW Current. The current flowing into an
output which is in the LOW state.
IOS
Output Short Circuit Current. The current flowing
out of an output in the HIGH state when that output
is shorted to ground (or other specified potential).
IOZ
Output high impedance current. The current
flowing into or out of a disabled output when
specified LOW or HIGH voltage is applied to that
output.
IOFF
Input/Output power–off leakage current. The
maximum leakage current into or out of the
input/output
transistors
when
forcing
the
input/output from 0V to 5.5V with VCC = 0V.
VCC
Supply Voltage. The range of power supply
voltages over which the device is guaranteed to
operate.
VIH
Input HIGH Voltage. The minimum input voltage
that is recognized as a DC HIGH level.
VIL
Input LOW Voltage. The maximum input voltage
that is recognized as a DC LOW level.
VOH
Output HIGH Voltage. The voltage at an output
conditioned HIGH with a specified output load and
VCC supply voltage.
VOL
Output LOW Voltage. The voltage at an output
conditioned LOW with a specified output load and
VCC supply voltage.
VOLP
Maximum (peak) voltage induced on a static LOW
output during switching of other outputs.
VOLV
Minimum (valley) voltage induced on a static LOW
output during switching of other outputs.
AC Characteristics
fmax Toggle Frequency/Operating Frequency – The
maximum rate at which clock pulses may be applied to a
sequential circuit. Above this frequency the device may cease
to function properly.
tPLH Propagation Delay Time – The time between the
specified reference points, on the input and output voltage
waveforms, with the output changing from the defined LOW
level to the defined HIGH level.
tPHL Propagation Delay Time – The time between the
specified reference points, on the input and output voltage
waveforms, with the output changing from the defined HIGH
level to the defined LOW level.
tw Pulse Width – The time between specified amplitude
points of the leading and trailing edges of a pulse.
th Hold Time – The interval immediately following the active
transition of the timing pulse (usually the clock pulse) or
following the transition of the control input to its latching level,
during which interval the data to be recognized must be
maintained at the input to ensure its continued recognition.
ts Setup Time – The interval immediately preceding the active
transition of the timing pulse (usually the clock pulse) or
preceding the transition of the control input to its latching level,
during which interval the data to be recognized must be
maintained at the input to ensure its recognition.
tPHZ Output Disable Time (of a 3–state Output) from HIGH
Level – The time between specified levels on the input and a
voltage 0.3V below the steady state output HIGH level with the
3–state output changing from the defined HIGH level to a high
impedance (OFF) state.
tPLZ Output Disable Time (of a 3–state Output) from LOW
Level – The time between specified levels on the input and a
voltage 0.3V above the steady state output LOW level with the
3–state output changing from the defined LOW level to a high
impedance (OFF) state.
tPZH Output Enable Time (of a 3–state Output) to a HIGH
Level – The time between the specified levels of the input and
output voltage waveforms with the 3–state output changing
from a high impedance (OFF) state to a HIGH level.
tPZL Output Enable Time (of a 3–state Output) to a LOW
Level – The time between the specified levels of the input and
output voltage waveforms with the 3–state output changing
from a high impedance (OFF) state to a LOW level.
trec Recovery Time – The time between the specified level on
the trailing edge of an asynchronous input control pulse and
the same level on a synchronous input (clock) pulse such that
the device will respond to the synchronous input.
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