參數(shù)資料
型號(hào)： MC74LCX00SD
廠商： ON SEMICONDUCTOR
元件分類： 門電路
英文描述： 15 A 12-V Input Bus Termination Power Module for DDR/QDR Memory 10-DIP MODULE -40 to 85
中文描述： LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝： PLASTIC, SSOP-14
文件頁(yè)數(shù)： 17/40頁(yè)
文件大?。?/td> 350K
代理商： MC74LCX00SD
Design Considerations
MOTOROLA
LCX DATA
BR1339 — REV 3
22
Thevenin Termination
Thevenin terminations are also not generally recommended
due to their power consumption. Like parallel termination, a
DC path to ground is created by the terminating resistors. The
power consumption of a Thevenin termination will generally
not be a function of the signal duty cycle. Thevenin
terminations are more applicable for driving CMOS inputs
because they do not bias the output levels as paralleled
terminations do. It should be noted that lines with Thevenin
terminations should not be left floating since this will cause the
input levels to float between VCC or ground, increasing power
consumption.
LCX circuits have been designed to drive 50
transmission
lines over the full temperature range.
LCX devices also feature balanced totem pole output
structures to allow equal source and sink current capability.
This provides balanced edge rates and equal rise and fall
times. Balanced drive capability and transition times
eliminates the need to calculate two different delay times for
each signal path and the requirement to correct signal polarity
for the shortest delay time.
Noise Effects
LCX offers excellent noise immunity. However, even the
most advanced technology alone cannot eliminate noise
problems. Good circuit board layout techniques are essential
to take full advantage of the superior performance of LCX
circuits.
Well–designed
circuit
boards
also
help
eliminate
manufacturing and testing problems.
Another recommended practice is to segment the board
into a high–speed area, a medium–speed area and a low–
speed area. The circuit areas with high current requirements
(i.e., buffer circuits and high–speed logic) should be as close
to the power supplies as possible; low–speed circuit areas can
be furthest away.
Decoupling capacitors should be adjacent to all buffer
chips; they should be distributed throughout the logic: one
capacitor per chip. Transmission lines need to be terminated
to keep reflections minimal. To minimize crosstalk, long signal
lines should not be close together.
Crosstalk
The problem of crosstalk and how to deal with it is
becoming more important as system performance and board
densities increase. Crosstalk is the capacitive coupling of
signals from one line to another. The amplitude of the noise
generated on the inactive line is directly related to the edge
rates of the signal on the active line, the proximity of the two
lines and the distance that the two lines are adjacent.
Crosstalk has two basic causes. Forward crosstalk,
Figure 16, is caused by the wavefront propagating down the
printed circuit trace at two different velocities. This difference
in velocities is due to the difference in the dielectric constants
of air (
∈r = 1) and epoxy glass (∈r = 4.7). As the wave
propagates down the trace, this difference in velocities will
cause one edge to reach the end before the other. This delay
is the cause of forward crosstalk; it increases with longer trace
length, so consequently the magnitude of forward crosstalk
will increase with distance.
Reverse crosstalk, Figure 17, is caused by the mutual
inductance and capacitance between the lines which is a
transformer action. Reverse crosstalk increases linearly with
distance up to a critical length. This critical length is the
distance that the signal can travel during its rise or fall time.
Although crosstalk cannot be totally eliminated, there are
some design techniques that can reduce system problems
resulting from crosstalk. LCX’s industry–leading noise
margins makes it easier to design systems immune to
crosstalk–related problems.
TIME (ns) (5.0 ns/DIV)
Figure 16. Forward Crosstalk on PCB Traces
0.0 V
VOL
T
AGE
(V)
Key
Vertical Scale
Horizontal Scale
Active Driver
1.0 V/Div
50 ns/Div
Forward Crosstalk
0.2 V/Div
5.0 ns/Div
Active Receiver
1.0 V/Div
5.0 ns/Div
This figure shows traces taken on a test fixture designed to exaggerate the
amplitude of crosstalk pulses.
相關(guān)PDF資料
PDF描述
MC74LCX02D 15 A 12-V Input Bus Termination Power Module for DDR/QDR Memory 10-DIP MODULE -40 to 85
MC74LCX02M 0.8 to 1.8 V 18-A, 12-V Input Non-Isolated Wide-Adjust Module 10-DIP MODULE -40 to 85
MC74LCX02 15 A 12-V Input Bus Termination Power Module for DDR/QDR Memory 10-DIP MODULE -40 to 85
MC74LCX540DWR2 LVC/LCX/Z SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20
MC74LCX646DTR2 LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC74LCX02D 功能描述:邏輯門 2-3.6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
MC74LCX02DG 功能描述:邏輯門 2-3.6V Quad 2-Input NOR RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
MC74LCX02DR2 功能描述:邏輯門 2-3.6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
MC74LCX02DR2G 功能描述:邏輯門 2-3.6V Quad 2-Input NOR RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
MC74LCX02DT 功能描述:邏輯門 2-3.6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
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