參數(shù)資料
型號(hào)： MC74LCX00SD
廠商： ON SEMICONDUCTOR
元件分類： 門(mén)電路
英文描述： 15 A 12-V Input Bus Termination Power Module for DDR/QDR Memory 10-DIP MODULE -40 to 85
中文描述： LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14
封裝： PLASTIC, SSOP-14
文件頁(yè)數(shù)： 11/40頁(yè)
文件大小： 350K
代理商： MC74LCX00SD
LCX Applications Information
LCX DATA
BR1339 — REV 3
17
MOTOROLA
Interfacing 5V–CMOS to Pure 3.3V Logic
(No 5V–Tolerance)
When the interface is a 5V CMOS device and a 3.3V
CMOS device
without 5V–tolerance, the problem is much the
same as with the 5V–TTL interface–but worse. The output of
the 5V device must be reduced or large currents will flow into
the 3.3V device. This type of interface is simply not
recommended.
Interfacing Pure 3.3V Logic to 5V Inputs
(No 5V Output Tolerance)
Interfacing 3.3V CMOS to 5V–TTL inputs can be done
directly. LVCMOS/LVTTL output specifications and 5V–TTL
input specifications are compatible. However, when
interfacing pure 3.3V parts (no 5V–tolerance) to a 5V bus
there is no protection against 5V signals when the 3.3V
output is disabled. If the 5V bus voltage levels exceed the
VCC of the 3.3V device, leakage current into the 3.3V device
will occur–loading the bus. Also, be aware of 5V buses with
pull–up resistors. If pull–up resistors are used then pull–down
resistors may be necessary to compensate and reduce the
high voltage level to within the 0.5V + VCC range of the 3.3V
device. Interfacing a 3.3V CMOS output to a 5V CMOS input
is discouraged. The output swing of the 3.3V device is
insufficient to reliably drive the 5V CMOS device without the
assistance of a pull–up resistor. If a pull–up resistor to 5V
VCC is used to raise the input level to the required VIH=3.15V
(for VCC=5V, higher for higher VCCs) then a massive current
flow may result into the 3.3V device.
Interfacing to 5V–Tolerant LCX CMOS Logic
Many of the problems and concerns associated with pure
3.3V interface can be resolved simply by using 5V–tolerant
LCX CMOS Logic. LCX tolerates 5V–TTL or 5V CMOS levels
on its inputs. There is no inherent leakage path that can
damage the device or in any way adversely affect this
interface.
The 5V–tolerant output feature protects the 3.3V bus from
high signal excursions on the 5V bus when the 3.3V bus is
inactive (3–State). Only LCX devices with 3–State capability
have 5V–tolerant outputs. Gates and MSI products without
3–State have 5V–tolerant inputs but not 5V–tolerant outputs.
When an LCX device is enabled, the 5V output tolerance is
not active and will not protect the LCX device in cases of bus
contention. Care must be taken to ensure that the LCX
device is 3–Stated when there are 5V signals present on the
bus.
Five volt signals can also be caused by the use of pull–ups
on the 5V bus. Similarly, certain 5V devices with internal
pull–ups may cause leakage current into an LCX enabled
output. Pay close attention to the 5V device input
specification to see if there are input pull–ups to a 5V supply.
LCX can drive a 5V–TTL input even if that input has an
internal pull–up, but the user should be aware that when
driving this type of input, some leakage current into the low
voltage supply will occur. The value of this current, IO, is
simply the 5V supply voltage value minus the 3.3V supply
voltage value divided by the pull–up resistor value.
(IO=(VCC5–VCC3)/Rpu).Ifthepull–upresistoris10Kohmsfor
example, the resultant current would be 1.7V/10K=170
A
per output. In this case, there would be no reliability concern.
The specified Absolute Maximum ICC/IGND Current (100mA
per supply/ground pin) must also be considered. For an octal
device, the current resulting from a pull–up to 5V must be
limited to 100mA/8 outputs = 12.5mA/output. 12.5mA, using
5V and 3.3V supplies, would necessitate limiting the pull–up
value to 136 ohms. Not until the 12.5mA/output value is
approached would there begin to be a chip reliability concern.
It is assumed that a low–voltage design power budget would
be spent long before the Absolute Maximum ICC/IGND
Current specification would come into play.
An LCX output is not recommended to drive a 5V CMOS
input. As noted in the previous section, the VOH level of the
LCX output is not High enough to reliably drive a 5V CMOS
input. (Either an open–drain output device or dual supply
translator is recommended to drive a 5V CMOS input.)
LCX Makes Power Management Easy
LCX also offers an advanced feature which can be used to
isolate powered–down subsystems from active 3.3V or 5V
buses. The LCX’ IOFF specification guarantees, when the
LCX’ VCC = 0V and the voltage present on the LCX’ output,
VO, is 5.5V or less, that the LCX’ output will sink less than
10
A (typically the value is < 1A). In other words, when VCC
= 0V, LCX is still 5V–tolerant on both the inputs and outputs.
Using this feature a system designer can use LCX to buffer
powered–down sections of a board, from active sections,
easily implementing advanced power manage– ment. See
Figure 13.
相關(guān)PDF資料
PDF描述
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MC74LCX02DG 功能描述:邏輯門(mén) 2-3.6V Quad 2-Input NOR RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
MC74LCX02DR2 功能描述:邏輯門(mén) 2-3.6V Quad 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
MC74LCX02DR2G 功能描述:邏輯門(mén) 2-3.6V Quad 2-Input NOR RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel
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