參數(shù)資料
型號(hào)： MC705L16CFUE
廠商： Freescale Semiconductor
文件頁數(shù)： 73/146頁
文件大?。?/td> 0K
描述： IC MCU 8BIT EPROM 80-QFP
標(biāo)準(zhǔn)包裝： 84
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SPI
外圍設(shè)備： LCD，POR，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-QFP
包裝： 托盤
Memory Map
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
32
Freescale Semiconductor
2.4.3 Open-Drain Output Control Register 1
DWOMH — Port D Open-Drain Mode (H)
When this bit is set, the upper four bits of port D are configured as open-drain outputs if these bits are
selected as port D output by the PDH bit in the LCDCR. This bit is cleared on reset.
DWOML — Port D Open-Drain Mode (L)
When this bit is set, the lower three bits of port D are configured as open-drain outputs if the
corresponding BPx pin is not used by the LCD driver. This bit is cleared on reset.
EWOMH — Port E Open-Drain Mode (H)
When this bit is set, the upper four bits of port E (that are configured as I/O output by the PEH bit in
the LCDCR) are configured as open-drain outputs. This bit is cleared on reset.
EWOML — Port E Open-Drain Mode (L)
When this bit is set, the lower four bits of port E (that are configured as I/O output by the PEL bit in the
LCDCR) are configured as open-drain outputs. This bit is cleared on reset.
Bits 3 and 2 — Reserved
These bits are not used and always return to logic 0.
AWOMH — Port A Open-Drain Mode (H)
When this bit is set, the upper four bits of port A that are configured as output (corresponding to the
DDRA bit set) become open-drain outputs. This bit is cleared on reset.
AWOML — Port E Open-Drain Mode (L)
When this bit is set, the lower four bits of port A that are configured as output (corresponding DDRA
bit set) become open-drain outputs. This bit is cleared on reset.
2.4.4 Open-Drain Output Control Register 2
Bits 7 and 6 — Reserved
These bits are not used and always read as logic 1. When configured as output, PC6 and PC7 are
always open drain.
Address:
Option Map — $000A
Bit 7
654321
Bit 0
Read:
DWOMH
DWOML
EWOMH
EWOML
0
AWOMH
AWOML
Write:
Reset:
00000000
Figure 2-7. Open-Drain Output Control Register 1 (WOM1)
Address:
Option Map — $000B
Bit 7
654321
Bit 0
Read:
1
CWOM5
CWOM4
CWOM3
CWOM2
CWOM1
CWOM0
Write:
Reset:
11000000
Figure 2-8. Open-Drain Output Control Register 2 (WOM2)
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