參數資料
型號: MC705L16CFUE
廠商: Freescale Semiconductor
文件頁數: 127/146頁
文件大?。?/td> 0K
描述: IC MCU 8BIT EPROM 80-QFP
標準包裝: 84
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SPI
外圍設備: LCD,POR,WDT
輸入/輸出數: 16
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: OTP
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-QFP
包裝: 托盤
Timer 1
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
81
IEDG — Input Edge
The value of the input edge determines which level transition on the TCAP pin will trigger free-running
counter transfer to the input capture register.
Reset does not affect the IEDG bit.
0 = Negative edge
1 = Positive edge
Bits 2–4 — Not Used
Always read logic 0
OLVL — Not Used
Always read logic 0
9.2.5 Timer Status Register
The TSR is a read-only register containing three status flag bits.
ICF — Input Capture Flag
0 = Flag cleared when TSR and input capture low register ($15) are accessed
1 = Flag set when selected polarity edge is sensed by input capture edge detector
OC1F — Output Compare 1 Flag
0 = Flag cleared when TSR and output compare low register ($17) are accessed
1 = Flag set when output compare register contents match the free-running counter contents
TOF — Timer Overflow Flag
0 = Flag cleared when TSR and counter low register ($19) are accessed
1 = Flag set when free-running counter transition from $FFFF to $0000 occurs
Bits 0–4 — Not Used
Always read logic 0
Accessing the timer status register satisfies the first condition required to clear status bits. The remaining
step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running counter at
random times to measure an elapsed time. Without incorporating the proper precautions into software,
the timer overflow flag could unintentionally be cleared if:
1.
The timer status register is read or written when TOF is set.
2.
The LSB of the free-running counter is read but not for the purpose of servicing the flag.
The counter alternate register at address $1A and $1B contains the same value as the free-running
counter (at address $18 and $19); therefore, this alternate register can be read at any time without
affecting the timer overflow flag in the timer status register.
Address:
$0013
Bit 7
654321
Bit 0
Read:
ICF
OC1F
TOF
00000
Write:
Reset:
U
00000
= Unimplemented
U = Unaffected
Figure 9-4. Timer Status Register (TSR)
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