參數(shù)資料
型號(hào)： MC68LC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 75/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Signal Description
2-4
M68060 USER’S MANUAL
MOTOROLA
nals are examined to determine whether the processor should invalidate matching cache
entries to maintain cache coherency.
2.1.2 Cycle Long-Word Address (CLA)
This active-low input signal controls the operation of A3 and A2 during bus cycles. Following
each clock-enabled clock edge in which CLA is asserted, the long-word address for each of
the four transfers encoded on A3 and A2 will increment in a circular wraparound fashion. If
CLA is negated during a clock-enabled clock edge, the values on A3 and A2 will not change.
It is not necessary to synchronize CLA with TA.
2.2 DATA BUS (D31–D0)
These three-state bidirectional signals provide the general-purpose data path between the
MC68060 and all other devices. The data bus can transfer 8, 16, or 32 bits of data per bus
transfer. During a burst bus cycle, the 128 bits of line information are transferred using four
32-bit transfers.
2.3 TRANSFER ATTRIBUTE SIGNALS
The following paragraphs describe the transfer attribute signals, which provide additional
information about the bus transfer cycle. Refer to Section 7 Bus Operation for detailed
information about the relationship of the transfer attribute signals to bus operation.
2.3.1 Transfer Cycle Type (TT1, TT0)
The processor drives these three-state signals to indicate the type of access for the current
bus cycle. During bus cycle transfers by an alternate bus master when the processor is
allowed to snoop bus transactions, TT1 is sampled. Only normal and MOVE16 accesses
can be snooped. Table 2-2 lists the definition of the TTx encoding. The acknowledge access
(TT1 = 1 and TT0 = 1) is used for interrupt acknowledge, breakpoint acknowledge, and low-
power stop broadcast bus cycles.
2.3.2 Transfer Cycle Modifier (TM2–TM0)
These three-state outputs provide supplemental information for each transfer cycle type.
Table 2-3 lists the encoding for normal (TTx = 00) and MOVE16 (TTx = 01) transfers, and
Table 2-4 lists the encoding for alternate access transfers (TTx = 10). For interrupt acknowl-
edge transfers, the TMx signals carry the interrupt level being acknowledged. For breakpoint
Table 2-2. Transfer-Type Encoding
TT1
TT0
Transfer Type
0
Normal Access
0
1
MOVE16 Access
10
Alternate Logical Function Code Access, De-
bug Access
11
Acknowledge Access, Low-Power Stop
Broadcast
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