參數(shù)資料
型號： MC68LC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 114/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Memory Management Unit
MOTOROLA
M68060 USER’S MANUAL
4-17
When the MC68060 has completed a normal table search, it examines the PDT field of the
last entry fetched from the page tables. If the PDT field contains an indirect ($2) encoding,
it indicates that the address contained in the highest order 30 bits of the descriptor is a
pointer to the page descriptor that is to be used to map the logical address. The processor
then fetches the page descriptor from this address and uses the physical address field of
the page descriptor as the physical mapping for the logical address.
The page descriptor located at the address given by the indirect descriptor must not have a
PDT field with an indirect encoding (it must be either a resident descriptor or invalid). Oth-
erwise, the descriptor is treated as invalid, and the MC68060 takes an access error excep-
tion.
4.2.4.2 TABLE SHARING BETWEEN TASKS. More than one task can share a pointer- or
page-level table by placing a pointer to a shared table in the address translation tables. The
upper (nonshared) tables can contain different write-protected settings, allowing different
tasks to use the memory areas with different write permissions. In Figure 4-14, two tasks
share the memory translated by the table at the pointer table level. Task A cannot write to
the shared area; task B, however, has the W-bit clear in its pointer to the shared table so
that it can read and write the shared area. Also, the shared area appears at different logical
addresses for each task. Figure 4-14 illustrates shared tables in a translation table structure.
4.2.4.3 TABLE PAGING. The entire translation table for an active task need not be resident
in main memory. In the same way that only the working set of pages must be allocated in
main memory, only the tables that describe the resident set of pages need be available.
Placing the invalid code ($0 or $1) in the UDT field of the table descriptor that points to the
absent table(s) implements this paging of tables. When a task attempts to use an address
that an absent table would translate, the MC68060 is unable to locate a translation and takes
an access error exception when the access is needed (immediately for operand accesses
and when the instruction is needed for instructions).
The operating system determines that the invalid code in the descriptor corresponds to non-
resident tables. This determination can be facilitated by using the unused bits in the descrip-
tor to store status information concerning the invalid encoding. The MC68060 does not
interpret or modify an invalid descriptor’s fields except for the UDT field. This interpretation
allows the operating system to store system-defined information in the remaining bits. Infor-
mation typically stored includes the reason for the invalid encoding (tables paged out, region
unallocated, etc.) and possibly the disk address for nonresident tables. Figure 4-15 illus-
trates an address translation table in which only a single page table (table $15) is resident;
all other page tables are not resident.
4.2.4.4 DYNAMICALLY ALLOCATED TABLES. Similar to paged tables, a complete trans-
lation table need not exist for an active task. The operating system can dynamically allocate
the translation table based on requests for access to particular areas.
Since it is difficult and less efficient to predict and reserve memory in advance for a task, an
operating system may choose to allocate no memory for a task until a demand is made
requesting access. This access may be to a previously unused area or for data that is no
longer resident in memory. If the access error handler adds to and updates the translation
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