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Bus Operation
4-42
MC68360 USER’S MANUAL
EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated
address space. The timer asserts BERR after timeout (case 3).
EXAMPLE B: A system uses error detection and correction on RAM contents. The designer
may:
1. Delay DSACKx until data is verified and assert BERR and HALT simultaneously to in-
dicate to the QUICC to automatically retry the error cycle (case 5), or, if data is valid,
assert DSACKx (case 1).
2. Delay DSACKx until data is verified and assert BERR with or without DSACKx if data
is in error (case 3). This initiates exception processing for software handling of the con-
dition.
3. Return DSACKx prior to data verification; if data is invalid, BERR is asserted on the
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
4. Return DSACKx prior to data verification; if data is invalid, assert BERR and HALT on
the next clock cycle (case 6). The memory controller can then correct the RAM prior
to or during the automatic retry.
NOTES:
N —The number of current even bus state (e.g., S2, S4, etc.)
A —Signal is asserted in this bus state
NA —Signal is not asserted in this state
X —Don't care
S —Signal was asserted in previous state and remains asserted in this state
4.5.1 Bus Errors
BERR can be used to abort the bus cycle and the instruction being executed. BERR takes
precedence over DSACKx provided it meets the timing constraints described in Section 10
Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredict-
Table 4-8. DSACKx, BERR, and HALT Assertion Results
Case
Num
Control
Signal
Asserted on Rising
Edge of State
Result
N
N + 2
1
DSACKx
BERR
HALT
A
NA
S
NA
X
Normal cycle terminate and continue.
2
DSACKx
BERR
HALT
A
NA
A/S
S
NA
S
Normal cycle terminate and halt; continue when HALT negated.
3
DSACKx
BERR
HALT
NA/A
A
NA
X
S
NA
Terminate and take bus error exception, possibly deferred.
4
DSACKx
BERR
HALT
A
NA
X
A
NA
Terminate and take bus error exception, possibly deferred.
5
DSACKx
BERR
HALT
NA/A
A
A/S
X
S
Terminate and retry when HALT negated.
6
DSACKx
BERR
HALT
A
NA
X
A
Terminate and retry when HALT negated.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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