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Table of Contents
Paragraph
Title
Page
Number
xxiv
MC68360 USER’S MANUAL
9.8.1.11
MC68EC030 Caching Configuration......................................................9-79
9.8.1.12
Double Bus Fault ...................................................................................9-79
9.8.1.13
JTAG and Three-State...........................................................................9-79
9.8.1.14
QUICC Serial Ports................................................................................9-79
9.8.2
Memory Interfaces .................................................................................9-79
9.8.2.1
QUICC Memory Interface Pins ..............................................................9-80
9.8.2.2
Regular EPROM or Flash EPROM ........................................................9-80
9.8.2.3
Regular SRAM .......................................................................................9-82
9.8.2.4
EEPROM ...............................................................................................9-84
9.8.2.5
DRAM SIMM ..........................................................................................9-84
9.8.2.6
DRAM Devices.......................................................................................9-86
9.8.3
Software Configuration ..........................................................................9-86
9.8.3.1
Basic Initialization ..................................................................................9-86
9.8.3.2
Configuring the Memory Controller ........................................................9-87
9.8.4
Interfacing Multiple QUICCs to an MC68EC030....................................9-89
9.8.5
Using a Higher Speed MC68EC030 Master with the QUICC ................9-89
9.9
Putting a Background Debug Mode Connector on a Target Board .......9-90
Section 10
Electrical Characteristics
10.1
Maximum Ratings ..................................................................................10-1
10.2
Thermal Characteristics .........................................................................10-2
10.3
Power Considerations............................................................................10-2
10.4
AC Electrical Specification Definitions ...................................................10-3
10.5
DC Electrical Specifications ...................................................................10-5
10.6
AC Power Dissipation ............................................................................10-6
10.7
AC Electrical Specifications Control Timing...........................................10-7
10.8
External Capacitor for PLL.....................................................................10-8
10.9
Bus Operation AC Timing Specifications ...............................................10-9
10.9
Bus Operation AC Timing Specifications (Continued) .........................10-10
10.9
Bus Operation AC Timing Specifications (Continued) ........................10-11
10.9
Bus Operation AC Timing Specifications (Continued ..........................10-12
10.10
Bus Operation—DRAM Accesses AC Timing Specifications .............10-28
10.11
030/QUICC Bus Type Slave Mode Bus Arbitration AC Electrical Specifica-
tions
10-33
10.12
030/QUICC Bus Type Slave Mode Internal Read/Write/IACK
Asynchronous Cycles AC Electrical Specifications..............................10-36
10.14
030/QUICC Bus Type SRAM/DRAM Cycles AC Electrical Specifications10-
44
10.15
040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications10-49
10.16
040 Bus Type Slave Mode Internal Read/write/IACK Cycles AC Electrical
Specifications10-51
10.17
040 Bus Type SRAM/DRAM Cycles Ac Electrical Specifications .......10-56
10.18
IDMA AC Electrical Specifications ......................................................10-62
10.19
PIP/PIO AC Electrical Specifications ...................................................10-64
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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