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System Integration Module (SIM60)
6-20
MC68360 USER’S MANUAL
NOTE: If the PLL is enabled and the multiplication factor is less than or equal to 4, then CLKO2–CLKO1 is
synchronized to EXTAL.
6.6 BREAKPOINT LOGIC
The breakpoint logic provides an internal breakpoint address register (BKAR) and a break-
point control register (BKCR) that allow hardware breakpoints in a QUICC system. This
function is especially useful during in-field debugging activity when it is difficult to connect
an in-circuit emulator or logic analyzer to the target board. The use of the background mode
of the CPU32+, in combination with the breakpoint logic, provides a convenient and powerful
debugging capability.
NOTE
Emulator manufacturers use the QUICC breakpoint logic in their
QUICC emulator designs. Customers using emulators should
leave the breakpoint logic available for use by the emulator man-
ufacturer, and should not configure the breakpoint logic in their
application programs.
When a breakpoint match occurs, the BKPT line is asserted. This can cause a BKPT excep-
tion to the CPU32+, and will set a status bit in the IDMA or SDMA that can be used to gen-
erate a maskable interrupt. The maskable interrupt may or may not terminate IDMA or
SDMA activity, depending on the bus arbitration priority of the IDMA or SDMA as compared
to the interrupt level asserted.
NOTE
When the QUICC is configured for a 32-bit bus, the CPU32+ can
fetch two instructions simultaneously. Since there is only one
BKPT pin, the user cannot break on each instruction, but rather
must break on both, causing the BKPT exception to be taken af-
ter the first instruction and before the second. The internal
breakpoint logic, however, can assert a breakpoint for either in-
struction individually.
The breakpoint logic allows a great deal of flexibility in what constitutes a breakpoint match.
If more than one hardware breakpoint is required, then additional breakpoints may be gen-
erated externally in hardware and assert the BKPT pin.
Table 6-1. Default Operation Mode of the PLL
MODCK
1–0
PLL
Prescaled by
128
Multi. Factor
(MF + 1)
EXTAL Freq.
(Examples)
CLKIN to the
PLL
Initial Freq.
(VCO/2)
00
Disabled
Reserved
01
Enabled
No
1
>10 MHz
=EXTAL
10
Enabled
Yes
401
4.192 MHz
32.75 kHz
13.14 MHz
11
Enabled
No
401
32.768 kHz
13.14 MHz
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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