
Serial Communication Controllers (SCCs)
MC68360 USER’S MANUAL
Figure 7-72. Ethernet Interrupt Events Example;
7.10.23.21 ETHERNET MASK REGISTER (SCCM). The SCCM is referred to as the Ether-
net mask register when the SCC is operating as an Ethernet controller. It is a 16-bit read-
write register that has the same bit formats as the Ethernet event register. If a bit in the
Ethernet mask register is a one, the corresponding interrupt in the event register will be
enabled. If the bit is zero, the corresponding interrupt in the event register will be masked.
This register is cleared upon reset.
7.10.23.22 ETHERNET STATUS REGISTER (SCCS). This register is not valid for the
Ethernet protocol. The current state of the RENA and CLSN signals may be read in port C.
LINE IDLE
STORED IN RX BUFFER
FRAME
RECEIVED IN ETHERNET
TIME
RXD
LINE IDLE
STORED IN
TX BUFFER
CLSN
LINE IDLE
TXD
TENA
RXB
TXB
NOTES:
1. RXB event assumes receive buffers are 64 bytes each.
2. The RENA events, if required, must be programmed in the port C parallel I/O, not in the SCC itself.
3. The RXF interrupt may occur later than RENA due to receive FIFO latency.
LEGEND:
P = Preamble, SFD = Start Frame Delimiter, DA and SA = Source/Destination Address, T/L = Type/Length,
D = Data, and CR = CRC bytes.
NOTES:
1. TXB events assume the frame required two transmit buffers.
2. The GRA event assumes a GRACEFUL STOP TRANSMIT command was issued during frame transmission.
3. The TENA or CLSN events, if required, must be programmed in the port C parallel I/O, not in the SCC itself.
ETHERNET SCCE
EVENTS
HDLC SCCE
EVENTS
FRAME
TRANSMITTED BY ETHERNET
DA SA T/L
CR
D
RXF
P
RENA
SFD DA SA T/L
CR
D
P
TXB
GRA
SFD
F
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