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MC68360 USER’S MANUAL
7.13.9.1
Port B Assignment Registers (PBPAR) ...............................................7-356
7.13.9.2
Data Direction Register (PBDIR) .........................................................7-356
7.13.9.3
Data Register (PBDAT)........................................................................7-356
7.13.9.4
Open-Drain Register (PBODR)............................................................7-356
7.14
Parallel I/O Ports..................................................................................7-356
7.14.1
Parallel I/O Key Features.....................................................................7-357
7.14.2
Parallel I/O Overview ...........................................................................7-357
7.14.3
Port A Pin Functions ............................................................................7-357
7.14.4
Port A Registers...................................................................................7-359
7.14.4.1
Port A Open-Drain Register (PAODR).................................................7-359
7.14.4.2
Port A Data Register (PADAT).............................................................7-359
7.14.4.3
Port A Data Direction Register (PADIR) ..............................................7-359
7.14.4.4
Port A Pin Assignment Register (PAPAR) ...........................................7-359
7.14.5
Port A Examples ..................................................................................7-360
7.14.6
Port B Pin Functions ............................................................................7-362
7.14.7
Port B Registers...................................................................................7-363
7.14.7.1
Port B Open-Drain Register (PBODR).................................................7-363
7.14.7.2
Port B Data Register (PBDAT).............................................................7-364
7.14.7.3
Port B Data Direction Register (PBDIR) ..............................................7-364
7.14.7.4
Port B Pin Assignment Register (PBPAR) ...........................................7-364
7.14.8
Port B Example ....................................................................................7-365
7.14.9
Port C Pin Functions ............................................................................7-365
7.14.10
Port C Registers...................................................................................7-367
7.14.10.1
Port C Data Register (PCDAT) ............................................................7-368
7.14.10.2
Port C Data Direction Register (PCDIR) ..............................................7-368
7.14.10.3
Port C Pin Assignment Register (PCPAR)...........................................7-368
7.14.10.4
Port C Special Options (PCSO) ...........................................................7-368
7.14.10.5
Port C Interrupt Control Register (PCINT) ...........................................7-369
7.15
CPM Interrupt Controller (CPIC) ..........................................................7-369
7.15.1
Overview ..............................................................................................7-370
7.15.2
CPM Interrupt Source Priorities ...........................................................7-372
7.15.2.1
SCC Relative Priority ...........................................................................7-372
7.15.2.2
Highest Priority Interrupt ......................................................................7-372
7.15.2.3
Nested Interrupts .................................................................................7-373
7.15.3
Masking Interrupt Sources in the CPM ................................................7-374
7.15.4
Interrupt Vector Generation and Calculation........................................7-375
7.15.5
CPIC Programming Model ...................................................................7-377
7.15.5.1
CPM Interrupt Configuration Register (CICR)......................................7-377
7.15.5.2
CPM Interupt Pending Register (CIPR) ...............................................7-379
7.15.5.3
CPM Interrupt Mask Register (CIMR) ..................................................7-380
7.15.5.4
CPM Interrupt In-Service Register (CISR) ...........................................7-380
7.15.6
Interrupt Handler Examples .................................................................7-381
7.15.6.1
Example 1—PC6 Interrupt Handler .....................................................7-381
7.15.6.2
Example 2—SCC1 Interrupt Handler...................................................7-381
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Freescale Semiconductor, Inc.
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