參數(shù)資料
型號: MAX5978ETJ+
廠商: Maxim Integrated
文件頁數(shù): 37/38頁
文件大?。?/td> 2412K
描述: IC CTLR HOT-SWAP 32TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
類型: 熱交換控制器
應用: 刀峰式服務器,網(wǎng)絡應用設備
內(nèi)部開關:
電流限制: 可調(diào)
電源電壓: 2.7 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應商設備封裝: 32-TQFN-EP(5x5)
包裝: 管件
0 to 16V, Hot-Swap Controller with 10-Bit
Current, Voltage Monitor, and 4 LED Drivers
37
The slave generates a NACK at step 5 if the command
code is invalid. The command code must be in the 0x00
to 0x45 range. The internal address pointer returns
to 0x00 after incrementing from the highest register
address.
Receive Byte
The receive-byte protocol allows the master device to
read the register content of the device (see Figure 7).
The EEPROM or register address must be preset with a
send-byte protocol first. Once the read is complete, the
internal pointer increases by one. Repeating the receive
byte protocol reads the contents of the next address.
The receive-byte procedure follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a read
bit (high).
3) The addressed slave asserts an ACK on SDA.
4) The slave sends 8 data bits.
5) The slave increments its internal address pointer.
6) The master asserts an ACK on SDA and repeats
steps 4, 5 or asserts a NACK and generates a STOP
condition.
The internal address pointer returns to 0x00 after incre-
menting from the highest register address.
Address Pointers
Use the send-byte protocol to set the register address
pointers before read and write operations. For the con-
figuration registers, valid address pointers range from
0x00 to 0x45, and the circular buffer addresses are 0x46
to 0x49. Register addresses outside this range result in
a NACK being issued from the device.
Circular Buffer Read
The circular buffer read operation is similar to the
receive-byte operation. The read operation is triggered
after any one of the circular buffer base addresses is
loaded. During a circular buffer read, although all is
transparent from the external world, internally the autoin-
crement function in the I
2
C controller is disabled. Thus,
it is possible to read one of the circular buffer blocks
with a burst read without changing the virtual internal
address corresponding to the base address. Once the
master issues a NACK, the circular reading stops, and
the default functions of the I
2
C slave bus controller are
restored.
In 8-bit read mode, every I
2
C read operation shifts out
a single sample from the circular buffer. In 10-bit mode,
two subsequent I
2
C read operations shift out a single
10-bit sample from the circular buffer, with the high-order
byte read first, followed by a byte containing the right-
shifted 2 least-significant bits. Once the master issues a
NACK, the read circular buffer operation terminates and
normal I
2
C operation returns.
The data in the circular buffers is read back with the
next-to-oldest sample first, followed by progressively
more recent samples until the most recent sample is
retrieved, followed finally by the oldest sample (see
Table 54).
  Chip Information
PROCESS: BiCMOS
  Package Information
For the latest package outline information and land pat terns,
go to www.maxim-ic.com/packages. Note that a +, #, or
- in the package code indicates RoHS status only. Package
drawings may show a different suf fix character, but the drawing
pertains to the package regardless of RoHS status.
Table 54. Circular Buffer Readout Sequence
READ-OUT ORDER
1ST OUT
2ND OUT
&
48TH OUT
49TH OUT
50TH OUT
Chronological Number
1
2
&
48
49
0
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
32 TQFN-EP
T3255+4
21-0140
90-0012
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