參數(shù)資料
型號: MAX5978ETJ+
廠商: Maxim Integrated
文件頁數(shù): 15/38頁
文件大小: 2412K
描述: IC CTLR HOT-SWAP 32TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 熱交換控制器
應(yīng)用: 刀峰式服務(wù)器,網(wǎng)絡(luò)應(yīng)用設(shè)備
內(nèi)部開關(guān):
電流限制: 可調(diào)
電源電壓: 2.7 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 管件
0 to 16V, Hot-Swap Controller with 10-Bit
Current, Voltage Monitor, and 4 LED Drivers
15
Figure 1 shows the detailed logic operation of the hot-
swap enable signals EN1, EN2, and ON, as well as the
effect of various fault conditions.
An input undervoltage threshold control for enabling
the hot-swap channel can be implemented by placing
a resistive divider between the drain of the hot-swap
MOSFET and ground, with the midpoint connected to
ON. The turn-on threshold voltage for the channel is then:
V
EN
 = 0.6V x (R1 + R2)/R2
The maximum rating for the ON input is 6V; do not
exceed this value.
Startup
When all conditions for channel turn-on are met, the
external n-channel MOSFET switch is fully enhanced
with a typical gate-to-source voltage of 5V to ensure
a low drain-to-source resistance. The charge pump at
the GATE driver sources 5FA to control the output volt-
age turn-on voltage slew rate. An external capacitor
can be added from GATE to GND to further reduce the
voltage slew rate. Placing a 1kI resistor in series with
this capacitance prevents the added capacitance from
increasing the gate turn-off time. Total inrush current is
the load current summed with the product of the gate-
voltage slew rate dV/dt and the load capacitance.
To determine the output dV/dt during startup, divide
the GATE pullup current I
G(UP)
 by the gate-to-ground
capacitance. The voltage at the source of the external
MOSFET follows the gate voltage, so the load dV/dt is
the same as the gate dV/dt. Inrush current is the product
of the dV/dt and the load capacitance. The time to start
up t
SU
 is the hot-swap voltage V
S
 divided by the output
dV/dt.
Be sure to choose an external MOSFET that can handle
the power dissipated during startup. The inrush cur-
rent is roughly constant during startup and the voltage
drop across the MOSFET (drain to source) decreases
linearly as the load capacitance charges. The resulting
power dissipation is, therefore, roughly equivalent to a
single pulse of magnitude (V
S
 x inrush current)/2 and
Table 3a. Register Function
Table 3b. status1 Register Format
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
0x32
[1:0]
ON input state
1 = ON above 600mV channel enable threshold
0 = ON below 600mV channel enable threshold
Bit 0: ON input state
Bit 1: unused
[4]
Unused
[7:6]
Voltage critical behavior (PROT input)
00 = Assert ALERT upon UV/OV critical (same as UV/OV warning behavior)
01 = Assert ALERT and deassert PG upon UV/OV critical
10 = Assert ALERT, deassert PG, and shut down channel upon UV/OV critical
11 = (Not possible)
Description:
Fault-detection behavior (three-state PROT input) and ON input status register
Resister Title:
status1
Register Address:
0x32
RESET
VALUE
R
R
R
R
R
R
R
R
prot[1]
prot[0]

Unused


Unused
ON

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0

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