參數(shù)資料
型號(hào): MAX5978ETJ+
廠商: Maxim Integrated
文件頁(yè)數(shù): 13/38頁(yè)
文件大?。?/td> 2412K
描述: IC CTLR HOT-SWAP 32TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 熱交換控制器
應(yīng)用: 刀峰式服務(wù)器,網(wǎng)絡(luò)應(yīng)用設(shè)備
內(nèi)部開(kāi)關(guān): 無(wú)
電流限制: 可調(diào)
電源電壓: 2.7 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 管件
0 to 16V, Hot-Swap Controller with 10-Bit
Current, Voltage Monitor, and 4 LED Drivers
13
  Detailed Description
The MAX5978 includes a set of registers that are
accessed through the I
2
C interface. Some of the reg-
isters are read only and some of the registers are read
and write registers that can be updated to configure the
device for a specific operation. See Tables 1a and 1b for
the register maps.
Hot-Swap Channel On-Off Control
Depending on the configuration of the EN1 and EN2
bits, when V
IN
 is above the V
UVLO
 threshold and the ON
input reaches its internal threshold, the device turns on
the external n-channel MOSFET for the hot-swap chan-
nel, allowing power to flow to the load. The channel is
enabled depending on the output of a majority function.
EN1, EN2, and ON are the inputs to the majority function
and the channel is enabled when two or more of these
inputs are 1:
(Channel enabled) = (EN1 x EN2) + (EN1 x ON) +
  (EN2 x ON)
Inputs ON and EN2 can be set externally; the initial state
of the EN2 bit in register chxen is set by the state of the
HWEN input when V
IN
 rises above V
UVLO
. The ON input
connects to an internal precision analog comparators
with a 0.6V threshold. Whenever V
ON
 is above 0.6V, the
ON bit in register status1[0] is set to 1. Inputs EN1 and
EN2 can be set using the I
2
C interface; the EN1 bit has
a default value of 0. This makes it possible to enable or
disable the hot-swap channel with or without using the
I
2
C interface (see Tables 2, 3a, and 3b).
Table 1a. Register Address Map (Channel Specific)
REGISTER
NAME
DESCRIPTION
REGISTER
NUMBER
RESET
VALUE
READ/
WRITE
adc_cs_msb
High 8 bits ([9:2]) of latest current-signal ADC result
0x00
0x00
R
adc_cs_lsb
Low 2 bits ([1:0]) of latest current-signal ADC result
0x01
0x00
R
adc_mon_msb
High 8 bits ([9:2]) of latest voltage-signal ADC result
0x02
0x00
R
adc_mon_lsb
Low 2 bits ([1:0]) of latest voltage-signal ADC result
0x03
0x00
R
min_cs_msb
High 8 bits ([9:2]) of current-signal minimum value
0x08
0xFF
R
min_cs_lsb
Low 2 bits ([1:0]) of current-signal minimum value
0x09
0x03
R
max_cs_msb
High 8 bits ([9:2]) of current-signal maximum value
0x0A
0x00
R
max_cs_lsb
Low 2 bits ([1:0]) of current-signal maximum value
0x0B
0x00
R
min_mon_msb
High 8 bits ([9:2]) of voltage-signal minimum value
0x0C
0xFF
R
min_mon_lsb
Low 2 bits ([1:0]) of voltage-signal minimum value
0x0D
0x03
R
max_mon_msb
High 8 bits ([9:2]) of voltage-signal maximum value
0x0E
0x00
R
max_mon_lsb
Low 2 bits ([1:0]) of voltage-signal maximum value
0x0F
0x00
R
uv1th_msb
High 8 bits ([9:2]) of undervoltage warning (UV1) threshold
0x1A
0x00
R/W
uv1th_lsb
Low 2 bits ([1:0]) of undervoltage warning (UV1) threshold
0x1B
0x00
R/W
uv2th_msb
High 8 bits ([9:2]) of undervoltage critical (UV2) threshold
0x1C
0x00
R/W
uv2th_lsb
Low 2 bits ([1:0]) of undervoltage critical (UV2) threshold
0x1D
0x00
R/W
ov1thr_msb
High 8 bits ([9:2]) of overvoltage warning (OV1) threshold
0x1E
0xFF
R/W
ov1thr_lsb
Low 2 bits ([1:0]) of overvoltage warning (OV1) threshold
0x1F
0x03
R/W
ov2thr_msb
High 8 bits ([9:2]) of overvoltage critical (OV2) threshold
0x20
0xFF
R/W
ov2thr_lsb
Low 2 bits ([1:0]) of overvoltage critical (OV2) threshold
0x21
0x03
R/W
oithr_msb
High 8 bits ([9:2]) of overcurrent warning threshold
0x22
0xFF
R/W
oithr_lsb
Low 2 bits ([1:0]) of overcurrent warning threshold
0x23
0x03
R/W
dac_fast
Fast-comparator threshold DAC setting
0x2E
0xBF
R/W
cbuf_ba_v
Base address for block read of 50-sample voltage-signal data buffer
0x46

R
cbuf_ba_i
Base address for block read of 50-sample current-signal data buffer
0x47

R
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