參數(shù)資料
型號: MAX5938LEEE+
廠商: Maxim Integrated
文件頁數(shù): 24/26頁
文件大?。?/td> 915K
描述: IC HOT-SWAP CTRLR -48V 16-QSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
類型: 熱交換控制器
應用: 通用
內部開關:
電源電壓: -10 V ~ -80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-QSOP
包裝: 管件
At any time (t) the V
OUT
fraction of V
OUT
(max) is:
V
OUT
(t) / [(dV/dt) x ?/DIV>
C
] = (1-e
(-t / 腖,eqv)
)
If V
OUT
(t) is measured at time t, then the equivalent
time constant of the load is found from:
?/DIV>
L,eqv
= -t / ln(1  V
OUT
/ [(dV/dt) x ?/DIV>
C
])
As mentioned earlier, several measurements of V
OUT
at times t1, t2, t3, and t4 should be made during the
ramp. Each of these may result in slightly different val-
ues of ?/DIV>
L,eqv
and all values should then be averaged.
In making the measurements, the V
IN
ramp duration
should be such that V
OUT
reaches 2 or 3 times the
selected V
SC
. The ramp tests should include three
ramp rates: V
SC
/ ?/DIV>
C
, 2 x V
SC
/ ?/DIV>
C
, and 4 x V
SC
/ ?/DIV>
C
.
The values of ?/DIV>
L,eqv
may vary over the range of slew
rates due to measurement error, nonlinear dynamics in
the load, and due to the fact that Equation 1 is a simpli-
fication from a higher order dynamic system. The
resulting range of ?/DIV>
L,eqv
values should be used to vali-
date the performance of the final design.
Having ?/DIV>
C
, ?/DIV>
L,eqv
, R
STEP
, and C
STEP
in a graphical
analysis using Equation 1 and Equation 2 can verify the
step monitor function by displaying the relative timing
of t
CB
, t
STEP
, and t
SC
, which are the times when V
CB
,
V
STEP_MON
, and V
SC
voltage thresholds are exceeded.
A simple Excel spreadsheet for this purpose can be
supplied by Maxim upon request. Figures 23, 24, and
25 graphically verify a particular solution over 3
decades of V
IN
ramp rates. In addition, Figure 25 veri-
fies that this solution will block all circuit-breaker and
short-circuit faults for even the lowest V
IN
ramp that will
cause V
OUT
to exceed V
CB
.
-48V Hot-Swap Controller with V
IN
Step Immunity,
No R
SENSE
, and Overvoltage Protection
24   ______________________________________________________________________________________
Figure 24. V
OUT
Response to V
IN
Ramp of 30V/ms
V
OUT
 RESPONSE TO V
IN
 RAMP OF 30V/ms
TIME (祍)
A
B
t
CB
E
F
C
D
A = V
IN
 (GND - V
EE
)
B = V
STEP_MON
C = V
OUT
D = V
STEP,TH
E = V
CB
F = V
SC
36
32
28
24
20
16
12
8
4
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0
40
t
SC
t
STEP
Figure 25. V
OUT
Response to V
IN
Ramp of 3V/ms
V
OUT
 RESPONSE TO V
IN
 RAMP OF 3V/ms
TIME (祍)
A = V
IN
 (GND - V
EE
)
B = V
STEP_MON
C = V
OUT
D = V
STEP,TH
E = V
CB
F = V
SC
400
300
100
200
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
0
500
A
B
D
E
F
C
t
STEP
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