參數(shù)資料
型號: MAX5938LEEE+
廠商: Maxim Integrated
文件頁數(shù): 17/26頁
文件大?。?/td> 915K
描述: IC HOT-SWAP CTRLR -48V 16-QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
類型: 熱交換控制器
應用: 通用
內(nèi)部開關:
電源電壓: -10 V ~ -80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-QSOP
包裝: 管件
-48V Hot-Swap Controller with V
IN
Step Immunity,
No R
SENSE
, and Overvoltage Protection
______________________________________________________________________________________   17
FAULT
MGT
CYCLE
GATE
LOW
t
CB_DLY
ESL
ESR
C
LOAD
C
LOAD
C
STEP_MON
R
STEP_MON
V
STEP_MON
R
DS,ON
GATE
V
EE
V
OUT
V
IN
STEP
STEP_MON
I
STEP
I
STEP_OS
GND
STEP
TH
STEP_DET
V
SC
V
CB
CB TRIP
MAX5938
SC TRIP
NOTE: V
SC
, V
CB
, V
STEPTH
, V
STEP_MON
, AND V
OUT
 ARE REFERENCED TO V
EE
.
Figure 16 is a functional diagram exhibiting the elements
of the MAX5938 involved in the step immunity function.
This functional diagram shows the parallel relationship
between V
OUT
and V
STEP-MON
. Each has an I*R compo-
nent establishing the DC level prior to a step. While it is
referred to as a V
IN
step, it is the dynamic response to a
finite voltage ramp that is of interest.
Given a positive V
IN
ramp with a ramp rate of dV/dt, the
approximate response of V
OUT
to V
IN
is:
V
OUT
(t) = (dV/dt) x ?/DIV>
C
x (1-e
(-t / 腖,eqv)
) + R
DS(ON)
I
LOAD
where ?/DIV>
C
= C
LOAD
x R
DS(ON)
and 腖,eqv is the equiva-
lent time constant of the load that must be found empir-
ically (see Appendix B).
Similarly, the response of STEP_MON to a V
IN
ramp is:
V
STEP_MON
(t) = (dV/dt) x ?/DIV>
STEP
x (1-e
(-t / 腟TEP)
) + 10礎
x R
STEP
where ?/DIV>
STEP
= R
STEP_MON
x C
STEP_MON
.
For proper step detection, V
STEP_MON
must exceed
STEP
TH
prior to V
OUT
reaching V
SC
or within 1.4ms of
V
OUT
reaching V
CB
(over all V
IN
ramp rates anticipated in
the application). V
STEP_MON
must be set below STEP
TH
with an adequate margin, V
STEP_MON
, to accommodate
the tolerance of both I
STEP_OS
(?%) and R
STEP_MON
.
R
STEP_MON
is typically set to 100k&, which gives a
V
STEP_MON
for a worst-case high of 0.36V.
The margin of V
OUT
, with respect to V
SC
and V
CB
, was
set when R
CB_ADJ
was selected as described in the
Setting the Circuit-Breaker and Short-Circuit Thresholds
section. This margin may be lower at one of the temper-
ature extremes and if so, that value should be used in
the following discussion. These margins will be called
V
CB
and V
SC
and they represent the minimum V
OUT
excursion required to trip the respective fault.
To set ?/DIV>
STEP
to block all V
CB
and V
SC
faults for any
ramp rate, find the ratio of V
STEP_MON
to V
CB
and
choose ?/DIV>
STEP
so:
?/DIV>
STEP
= 1.2 x ?/DIV>
C
x V
STEP_MON
/ V
CB
And since R
STEP_MON
= 100k&. This results in
C
STEP_MON
= ?/DIV>
STEP
/ 100k&.
After the first-pass component selection, if sufficient
timing margin exists (see Appendix B), it is possible but
not necessary to lower R
STEP_MON
below 100k& to
reduce the sensitivity of STEP_MON to V
IN
noise.
Figure 16. MAX5938 Step Immunity Functional Diagram
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