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參數(shù)資料
| 型號(hào)： | MAX5938LEEE+ |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 915K |
| 描述： | IC HOT-SWAP CTRLR -48V 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | -10 V ~ -80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 管件 |
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trol are in the linear range. If this is an issue, an external
resistor, R
GATE
, in series with gate of the MOSFET is rec-
ommended to prevent possible oscillation. It should be as
small as possible, e.g., 5& to 10&, to avoid impacting the
MOSFET turn-off performance of the MAX5938.
Layout Guidelines
To benefit from the temperature compensation designed
into the MAX5938, the part should be placed as close as
possible to the power MOSFET that it is controlling. The
V
EE
pin of the MAX5938 should be placed close to the
source pin of the power MOSFET and they should share
a wide trace. A common top layer plane would service
both the thermal and electrical requirements. The load-
probe current must be taken into account. If this current
is high, the layout traces and current-limiting resistor
must be sized appropriately. Stray inductance must be
minimized in the traces of the overall layout of the hot-
swap controller, the power MOSFET and the load capac-
itor. Starting from the board contacts, all high-current
traces should be short, wide, and direct. The potentially
high pulse current pins of the MAX5938 are GATE (when
pulling GATE low), load probe, and V
EE
. Because of the
nature of the hot-swap requirement no decoupling
capacitor is recommended for the MAX5938. Because
there is no decoupling capacitor, stray inductance may
result in excessive ringing at the GND pin during power-
up or during very rapid V
IN
steps. This should be exam-
ined in every application design since ringing at the
GND pin may exceed the absolute maximum supply rat-
ing for the part.
Input Transient Protection
During hot plug-in/unplug and fast V
IN
steps, stray
inductance in the power path may cause voltage ring-
ing above the normal input DC value, which may
exceed the absolute maximum supply rating. An input
transient such as that caused by lightning can also put
a severe transient peak voltage on the input rail. The
following techniques are recommended to reduce the
effect of transients:
1) Minimize stray inductance in the power path using
wide traces and minimize loop area including the
power traces and the return ground path.
2) Add a high-frequency (ceramic) bypass capacitor
on the backplane as close as possible to the plug-
in connector (Figure 20).
3) Add a 1k& resistor in series with the MAX5938s
GND pin and a 0.1礔 capacitor from GND to V
EE
to
limit transient current going into this pin.
Appendix A
GATE Cycles
The power-up GATE cycle, step GATE cycle, and the OV
GATE cycle are quite similar but have distinct differ-
ences. Understanding these differences may clarify
application issues.
GATE Cycle During Power-Up
The power-up GATE cycle occurs during the initial
power-up of the MAX5938 and the associated power
MOSFET and load. The power-up GATE cycle can
result in full enhancement or in a fault (all voltages are
relative to V
EE
).
Power-Up-to-Full-Enhancement Fault:
1) At the beginning of the power-up sequence to the
start of the power-up GATE cycle, the GATE is held
at V
EE
. Following a successful completion of the
load-probe test, GATE is held at V
EE
for an additional
350祍 and then is allowed to float for 650祍. At this
point, the GATE begins to ramp with 52礎(chǔ) charging
the gate of the power MOSFET. [GATE turn-on]
2) When GATE reaches the gate threshold voltage of
the power MOSFET, V
OUT
begins to ramp down
toward V
EE
. [V
OUT
ramp]
3) When V
OUT
ramps below 74% V
CB
, the GATE is
rapidly pulled to full enhancement and the power-
up GATE cycle is complete. 1.26ms after GATE is
pulled to full enhancement, PGOOD asserts. [Full
enhancement]
-48V Hot-Swap Controller with V
IN
Step Immunity,
No R
SENSE
, and Overvoltage Protection
20 ______________________________________________________________________________________
Figure 20. Protecting the MAX5938 Input from High-Voltage
Transients
0.1礔
0.1礔
1礔
1k&
100k&
V
EE
PGOOD
GND
BACKPLANE
48V
PLUG-IN CARD
OFF
ON
OV
STEP_MON
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5938LEEE+ | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5938LEEE+T | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5938LEEE-T | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5939AESA | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5939AESA+ | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
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