-48V Hot-Swap Controller with V
IN
Step Immunity,
No R
SENSE
, and Overvoltage Protection
______________________________________________________________________________________   13
Figure 10. Overvoltage Gate Cycle Without a Fault (t
OV
< 1.3ms)
V
IN
10V/div
V
PGOOD
10V/div
1ms/div
V
GATE
10V/div
V
OUT
10V/div
48V
Figure 11. Overvoltage Fault (t
OV
> 1.3ms)
V
IN
5V/div
V
PGOOD
50V/div
2ms/div
V
GATE
10V/div
V
OUT
50V/div
48V
t
OVREJ
Undervoltage Lockout (OFF and ON) and
OV Functions
OV, ON, and OFF provide an accurate means to set the
overvoltage, turn-on, and turn-off voltage levels. All three
are high-impedance inputs and by use of a 4-element
resistor-divider from GND to V
EE
, the user can set an
upper V
EE
threshold for triggering an overvoltage fault, a
middle threshold for turning the part on, and a lower
threshold for turning the part off.
The input voltage threshold at OFF is 1.25V. ON has
hysteresis with a rising threshold of 1.25V and a falling
threshold of 1.125V. The logic of the inputs is such that
both OFF and ON must be above their thresholds to
latch the part on. Both OFF and ON must be below their
respective thresholds to latch the part off, otherwise the
part stays in its current state. There is glitch rejection on
the ON input going low, which additionally requires that
ON remain below its falling threshold for 1.5ms to turn
off the part. A startup delay of 220ms allows contacts
and voltages to settle prior to initiating the startup
sequence. This startup delay is from a valid ON condi-
tion until the start of the load-probe test.
The OV input has hysteresis with a rising threshold of
1.25V and a falling threshold of 1.125V. The OV input
also has a rising fault transient delay of 1.5ms. When
OV rises above its threshold, an OV GATE cycle is
immediately initiated (see the GATE Cycles section in
Appendix A). The GATE output is brought to V
EE
with
about 300ns of propagation delay. If the OV input drops
below its falling threshold before the fault transient
delay of about 1.5ms, the device will not enter fault
management mode and the GATE output will ramp up
to fully enhance the external MOSFET (Figure 10).
Otherwise, an OV fault occurs (Figure 11). See the
Setting ON, OFF, and OV Voltage Levels section in the
Applications Information.
Output Voltage (V
OUT
)
Slew-Rate Control
The V
OUT
slew rate controls the inrush current required
to charge the load capacitor. The MAX5938 has a
default internal slew rate set for 9V/ms. The internal cir-
cuit establishing this slew rate accommodates up to
about 1000pF of reverse transfer capacitance (Miller
Capacitance) in the external power MOSFET without
effecting the default slew rate. Using the default slew
rate, the inrush current required to charge the load
capacitance is given by:
I
INRUSH
(mA) = C
LOAD
(礔) x SR (V/ms)
The slew rate can be reduced by adding an external
slew-rate control capacitor (C
SLEW
) from V
OUT
(the
drain of the power MOSFET) to the GATE output of the
MAX5938 (Figure 19). Values of C
SLEW
< 4700pF have
little effect on the slew rate because of the default slew-
rate control circuit. For C
SLEW
> 4700pF, the combina-
tion of C
SLEW
and reverse transfer capacitance of the
external power MOSFET dominate the slew rate. When
C
SLEW
> 4700pF, SR and C
SLEW
are inversely related
as follows (Figure 18):
SR (V/ms) = 23 / C
SLEW
(nF)
If the reverse transfer capacitance of the external
power MOSFET is large compared to the externally
added C
SLEW
, then it should be added to C
SLEW
in the
equation above.
See the Adjusting the V
OUT
Slew Rate section in the
Applications Information and Figure 18, which graphi-
cally displays the relation between C
SLEW
and slew
rate. This section discusses specific recommendations
for compensating power MOSFET parasitics that may
lead to oscillation when an external C
SLEW
is added.