-48V Hot-Swap Controller with V
IN
Step Immunity,
No R
SENSE
, and Overvoltage Protection
10   ______________________________________________________________________________________
the load. The short-circuit threshold voltage, V
SC
, is
twice V
CB
(V
SC
= 2 x V
CB
) and is set by adjusting the
resistance between CB_ADJ and V
EE
. There is an inter-
nal 2k& precision-trimmed resistor and an internal 50礎(chǔ)
current source at CB_ADJ, which results in the mini-
mum or default V
SC
of 100mV when CB_ADJ is con-
nected to V
EE
. The current source is temperature
compensated (increasing with temperature) to track the
normalized temperature coefficient of R
DS(ON)
for typical
power MOSFETs.
When the load current is increased during full enhance-
ment, this causes V
OUT
to exceed V
CB
but remains less
than V
SC
, and starts the 1.2ms circuit-breaker glitch
rejection timer. At the end of the glitch rejection period,
if V
OUT
still exceeds V
CB
, the GATE is immediately
pulled to V
EE
(330ns), PGOOD is deasserted, and the
part enters fault management. Alternatively, during full
enhancement when V
OUT
exceeds V
SC
, there is no
glitch rejection timer. GATE is immediately pulled to
V
EE
, PGOOD is deasserted, and the part enters fault
management.
The V
IN
step immunity provides a means for transitioning
through a large step increase in V
IN
with minimal back-
plane inrush current and without shutting down the load.
Without V
IN
step immunity (when the power MOSFET is
fully enhanced), a step increase in V
IN
will result in a
high inrush current and a large step in V
OUT
, which can
trip the circuit breaker.
With V
IN
step immunity, the STEP_MON input detects
the step before a short circuit is detected at V
OUT
and
alters the MAX5938 response to V
OUT
exceeding
V
SC
due to the step. The 1.25V voltage threshold at
STEP_MON and a 10礎(chǔ) current source at STEP_MON
allow the user to set the sensitivity of the step detection
with an external resistor to V
EE
. A capacitor is placed
between GND and the STEP_MON input, which in con-
junction with the resistor, sets the STEP_MON time
constant.
When a step is detected by the STEP_MON input rising
above its threshold (STEP
TH
), the overcurrent fault
management is blocked and remains blocked as long
as STEP
TH
is exceeded. When STEP
TH
is exceeded,
the MAX5938 takes no action until V
OUT
rises above
V
SC
or above V
CB
for the 1.2ms circuit-breaker glitch
rejection period. When either of these conditions
occurs, a step GATE cycle begins and the GATE is
immediately brought to V
EE
, which turns off the power
MOSFET to minimize the resulting inrush current surge
from the backplane. PGOOD remains asserted. GATE
is held at V
EE
for 350祍, and after about 1ms, begins to
ramp up, enhancing the power MOSFET in a controlled
manner as in the power-up GATE cycle. This provides a
controlled inrush current to charge the load capaci-
tance to the new supply voltage (see the GATE Cycles
section in Appendix A).
As in the case of the power-up GATE cycle, if V
OUT
drops to less than 74% of the programmed V
CB
, inde-
pendent of the state of STEP_MON, the GATE voltage is
rapidly pulled to full enhancement. PGOOD remains
asserted throughout the step (Figure 6). Otherwise, if the
STEP_MON input has decayed below its threshold but
V
OUT
remains above 74% of the programmed V
CB
(when GATE reaches 90% of full enhancement), a step-
to-fault-management fault has occurred. GATE is rapidly
pulled to V
EE
, turning off the power MOSFET and dis-
connecting the load; PGOOD is deasserted and the
MAX5938 enters the fault management mode (Figure 7).
Figure 6. MAX5938 Response to a Step Input with No Fault
(V
OUT
< 0.75V
CB
)
V
IN
5V/div
V
PGOOD
20V/div
2ms/div
V
GATE
10V/div
V
OUT
20V/div
I
IN
1A/div
C
LOAD
= 100礔
R
LOAD
= 100&
40V
Figure 7. MAX5938 Response to a Step Input Ending in a Fault
(V
OUT
> 0.75V
CB
)
V
IN
20V/div
V
PGOOD
50V/div
4ms/div
V
GATE
10V/div
V
OUT
50V/div
I
IN
5A/div
40V
20V
C
LOAD
= 100礔
R
LOAD
= 20&