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參數(shù)資料
| 型號(hào)： | MAX192BMJP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | Low-Power, 8-Channel, Serial 10-Bit ADC |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 201K |
| 代理商： | MAX192BMJP |
M
Low-Power, 8-Channel,
S erial 10-Bit ADC
_______________________________________________________________________________________
7
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.46V
REFERENCE
T/H
ANALOG
INPUT
MUX
SAR
ADC
IN
DOUT
SSTRB
V
DD
DGND
SCLK
DIN
CH0
CH1
CH2
CH3
CH4
CH7
CH6
CH5
AGND
AGND
REFADJ
VREF
OUT
REF
CLOCK
+4.096V
20k
≈
1.65
1
2
3
4
5
6
7
8
10
11
12
13
9
15
16
17
18
19
CS
SHDN
A
20
14
MAX192
Figure 3. Block Diagram
Detailed Desc ription
The MAX192 uses a successive-approximation conver-
sion technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX192.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7 and IN- is switched to AGND. In
differential mode, IN+ and IN- are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer
to Tables 1 and 2 to configure the channels.
In differential mode, IN- and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1μF capacitor from AIN- (the select-
ed analog input, respectively) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD
. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on C
HOLD
as a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
HOLD
from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is
simply AGND. This unbalances node ZERO at the input
of the comparator. The capacitive DAC adjusts during
the remainder of the conversion cycle to restore its
node ZERO to 0V within the limits of its resolution. This
action is equivalent to transferring a charge of
16pF x (V
IN
+ - V
IN
-) from C
HOLD
to the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
C
SWITCH
TRACK
T/H
SWITCH
10k
R
S
C
HOLD
HOLD
CAPACITIVE DAC
VREF
ZERO
COMPARATOR
–
+
16pF
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.
DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TOTHE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
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