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參數(shù)資料
| 型號： | MAX192BMJP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | Low-Power, 8-Channel, Serial 10-Bit ADC |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 201K |
| 代理商： | MAX192BMJP |
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX192. Figure 11b shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
__________ Applic ations Information
Power-On Reset
When power is first applied and if
SHDN
is not pulled
low, internal power-on reset circuitry will activate the
MAX192 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have been sta-
bilized, the internal reset time is 100μs and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if
CS
is low, the first logical 1 on
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT will shift out zeros.
Referenc e-Buffer Compensation
In addition to its shutdown function, the
SHDN
pin also
selects internal or external compensation. The compen-
sation affects both power-up time and maximum conver-
sion speed. Compensated or not, the minimum clock
rate is 100kHz due to droop on the sample-and-hold.
To select external compensation, float
SHDN
. See the
Typical Operating Circuit which uses a 4.7μF capacitor
at VREF. A value of 4.7μF or greater ensures stability
and allows operation of the converter at the full clock
speed of 2MHz. External compensation increases
power-up time (see the Choosing Power-Down Mode
section, and Table 5).
Internal compensation requires no external capacitor at
VREF, and is selected by pulling
SHDN
high. Internal
compensation allows for shortest power-up times, but is
only available using an external clock and reduces the
maximum clock rate to 400kHz.
M
Low-Power, 8-Channel,
S erial 10-Bit ADC
______________________________________________________________________________________
13
t
SDV
t
SSTRB
PD0 CLOCKED IN
t
STR
SSTRB
SCLK
CS
t
SSTRB
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
18
20
24
START
SEL2 SEL1 SEL0
BIP
DIF
PD1
PD0
B9
B8
B7
B0
S1
S0
ACQUISITION
1.5μs (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
10μs MAX
A/D STATE
2
3
5
6
7
9
10
11
19
21
22
23
t
CONV
Figure 8. External Clock Mode SSTRB Detailed Timing
Figure 9. Internal Clock Mode Timing
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