參數(shù)資料
型號(hào): M6MGB160S4BVP
廠商: Mitsubishi Electric Corporation
英文描述: CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-MCP
中文描述: 3.3的CMOS只快閃記憶體
文件頁數(shù): 27/30頁
文件大?。?/td> 257K
代理商: M6MGB160S4BVP
MITSUBISHI LSIs
Sep. 1999 , Rev.2.0
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144WORD BY 16-BIT / 524,288-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
M6MGB/T160S4BVP
AC ELECTRICAL CHARACTERISTICS
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
1TTL
CL
DQ
(1) TEST CONDITIONS
Input rise time and fall time
Reference level
Output loads
2.7V~3.6V
V
IH
=2.4V,V
IL
=0.4V
5ns
V
OH
=V
OL
=1.5V
Transition is measured
±
500mV from
steady state voltage.(for t
en
,t
dis
)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Supply voltage
Input pulse
Fig.1 Output load
Including scope and
jig capacitance
Output disable time after S-CE low
Output disable time after OE# high
Output enable time after S-CE high
Output enable time after OE# low
t
CR
t
a
(A)
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
a
(CE)
t
a
(OE)
t
dis
(CE)
t
dis
(OE)
t
en
(CE)
t
en
(OE)
t
V
(A)
(2) READ CYCLE
Symbol
Parameter
Limits
SRAM
Units
Max
Min
85
Read cycle time
Address access time
Chip select access time
Output enable access time
Data valid time after address
10
5
10
45
30
30
85
85
(3) WRITE CYCLE
t
su
(A-WH)
t
su
(CE)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
t
CW
t
w
(W)
t
su
(A)
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from WE# low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Limits
SRAM
Units
Max
Min
85
60
0
70
70
35
0
0
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to WE#
Output disable time from OE# high
Output enable time from WE# high
Output enable time from OE# low
30
30
5
5
27
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