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| 型號(hào)： | M5M4V4405CTP-7S |
| 廠(chǎng)商： | Mitsubishi Electric Corporation |
| 英文描述： | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| 中文描述： | 江戶(hù)（超頁(yè)模式）4194304位（1048576 - Word的4位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 8/27頁(yè) |
| 文件大?。?/td> | 293K |
| 代理商： | M5M4V4405CTP-7S |
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EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
M5M4V4405CJ,TP-6,-7,-6S,-7S
MITSUBISHI LSIs
Parameter
Symbol
Limits
Unit
Min
138
94
Max
Min
166
112
Max
Parameter
Symbol
Limits
Unit
Min
115
65
Max
Min
135
75
Max
Parameter
Symbol
Limits
Unit
Min
Max
20
Min
Max
25
RAS cycling, CAS= V
IH
t
RC
=min.
output open
Average supply current
from V
CC
operating
Average supply current
from V
CC
refreshing
Average supply current
from V
CC
Hyper-Page-Mode
Average supply current
from V
CAS before RAS refresh
mode
Symbol
Parameter
Limits
Typ
Min
Max
Unit
Test conditions
Test Mode Specification
(Note 31)
ELECTRICAL CHARACTERISTICS
(Ta=0~70C, V
CC
=3.3V±0.3V, V
SS
=0V, unless otherwise noted)
(Note 2)
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
I
CC1 (AV)
(Note 3,4,5)
mA
85
I
CC3 (AV)
I
CC4(AV)
I
CC6(AV)
(Note 3,5)
(Note 3,4,5)
(Note 3)
mA
mA
mA
85
75
85
75
75
65
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
75
Note 31: All previously specified electrical characteristics, switing characteristics, and timing requirements are applicable to that of test mode.
SWITCHING CHARACTERISTICS
(Ta=0~70C, V
CC
=3.3V±0.3V, V
SS
=0V, unless otherwise noted, see notes 6,14,15)
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
ns
ns
ns
ns
ns
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
35
38
20
65
40
43
25
75
20
35
23
15
53
10000
25
40
28
18
60
10000
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
ns
ns
ns
ns
ns
ns
ns
TIMING REQUIREMENTS
(Ta=0~70C, V
CC
=3.3V±0.3V, V
SS
=0V, unless otherwise noted, see notes 14,15)
Read and Refresh Cycles
t
RAS
t
CAS
t
CSH
t
RSH
t
RAL
t
CAL
t
RC
t
OCH
t
ORH
ns
ns
10000
10000
20
20
25
25
49
37
82
52
49
94
10000
62
47
97
62
62
112
10000
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
ns
ns
ns
ns
ns
ns
ns
ns
Read-Write and Read-Modify-Write Cycles
10000
10000
(Note 23)
(Note 24)
(Note 24)
(Note 24)
t
RWC
t
RAS
t
CAS
t
CSH
t
RSH
t
CWD
t
RWD
t
AWD
8
RAS, CAS cycling
t
RC
=t
WC
=min.
output open
RAS=V
IL
, CAS cycling
t
PC
=min.
output open
CAS before RAS refresh cycling
t
RC
=min.
output open
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Column address to RAS hold time
Column address to CAS hold time
RAS hold time after OE low
CAS hold time after OE low
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
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