參數(shù)資料
型號: M5M4V4405CTP-7S
廠商: Mitsubishi Electric Corporation
英文描述: EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
中文描述: 江戶(超頁模式)4194304位(1048576 - Word的4位)動態(tài)隨機(jī)存儲器
文件頁數(shù): 2/27頁
文件大?。?/td> 293K
代理商: M5M4V4405CTP-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
M5M4V4405CJ,TP-6,-7,-6S,-7S
MITSUBISHI LSIs
aRow
Column
Input/Output
Refresh
Remark
Hyper
Page
mode
identical
CAS before RAS refresh
Self refresh
*
RAS-only refresh
Hidden refresh
Operation
FUNCTION
In addition to normal read, write, and read-modify-write operations
the M5M4V4405CJ,TP provide, a number of other functions, e.g.,
Hyper Page mode, RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
RAS
CAS
OE
Inputs
W
Input
Output
Table 1 Input conditions for each mode
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
Stand-by
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
NAC
ACT
ACT
ACT
DNC
DNC
NAC
NAC
DNC
ACT
DNC
NAC
ACT
DNC
ACT
DNC
DNC
DNC
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
APD
APD
AP
AD
DNC
DNC
DNC
DNC
DNC
OPN
APD
APD
APD
DNC
OPN
DNC
DNC
DNC
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
OPN
YES
YES
YES
YES
YES
YES
YES
YES
NO
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
SENSE REFRESH
AMPLIFER & I /O CONTROL
ROW &
COLUMN
ADDRESS
BUFFER
BLOCK DIAGRAM
2
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ADDRESS INPUTS
V
CC
(3.3V)
V
SS
(0V)
OE
DQ
1
DQ
2
DQ
3
DQ
4
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
CAS
RAS
W
A
0
~ A
9
A
0
~
A
9
CLOCK GENERATOR
CIRCUIT
COLUMN DECODER
ROW
DECODER
MEMORY CELL
(4,194,304 BITS)
(4)
DATA IN
BUFFERS
(4)
DATA OUT
BUFFERS
DATA
INPUTS /
OUTPUTS
OUTPUT
ENABLE
INPUT
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