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| 型號(hào)： | M5M4V4405CTP-7S |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| 中文描述： | 江戶（超頁(yè)模式）4194304位（1048576 - Word的4位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 6/27頁(yè) |
| 文件大小： | 293K |
| 代理商： | M5M4V4405CTP-7S |
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EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
M5M4V4405CJ,TP-6,-7,-6S,-7S
MITSUBISHI LSIs
Parameter
Symbol
Limits
Unit
Min
133
89
Max
Min
161
107
Max
Parameter
Symbol
Limits
Unit
Min
110
60
10
48
10
Max
Min
130
70
13
55
13
Max
6
Write Cycle (Early Write and Delayed Write)
(Note 24)
10000
10000
10
0
10
10
10
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
13
0
13
13
13
0
13
t
WC
t
RAS
t
CAS
t
CSH
t
RSH
t
WCS
t
WCH
t
CWL
t
RWL
t
WP
t
DS
t
DH
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
Read-Write and Read-Modify-Write Cycles
(Note 23)
(Note 24)
(Note 24)
(Note 24)
t
RWC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
CWD
t
RWD
t
AWD
t
OEH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
Note 23:
t
RWC
is specified as
t
RWC(min )
=
t
RAC(max)
+
t
ODD(min)
+
t
RWL(min)
+
t
RP(min)
+4
t
T
.
@
24:
t
WCS
,
t
CWD
,
t
RWD
,
t
AWD
, and
t
CPWD
are specified as reference points only. If
t
WCS
≥
t
WCS(min)
the cycle is an early write cycle and the DQ pins will
remain high impedance throughout the entire cycle. If
t
CWD
≥
t
CWD(min)
,
t
RWD
≥
t
RWD(min)
,
t
AWD
≥
t
AWD(min)
and
t
CPWD
≥
t
CPWD (min)
(for fast page
mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above
condition (delayed write) of the DQ (at access time and until CAS or OE goes back to V
IH
) is indeterminate.
44
0
32
77
47
44
10000
10000
89
57
0
42
92
57
20
57
10000
10000
107
15
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before0 CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
OE hold time after W low
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