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參數(shù)資料
| 型號(hào)： | M59MR032C120ZC6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 32兆位的2Mb x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁(yè)數(shù)： | 22/49頁(yè) |
| 文件大?。?/td> | 352K |
| 代理商： | M59MR032C120ZC6T |
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M59MR032C, M59MR032D
Table 29. Asynchronous Read AC Characteristics
(TA = –40 to 85°C; VDD = VDDQ = 1.65V to 2.0V)
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
Symbol
Alt
Parameter
Test Condition
M59MR032
Unit
100
120
Min
Max
Min
Max
tAVAV
tRC
Address Valid to Next
Address Valid
E = VIL, G = VIL
100
120
ns
tAVLH
tAVAVDH
Address valid to Latch
Enable High
G = VIH
10
ns
tAVQV
tACC
Address Valid to Output
Valid (Random)
E = VIL, G = VIL
100
120
ns
tAVQV1
tPAGE
Address Valid to Output
Valid (Page)
E = VIL, G = VIL
45
ns
tEHQX
tOH
Chip Enable High to Output
Transition
G = VIL
00
ns
tEHQZ
(1)
tHZ
Chip Enable High to Output
Hi-Z
G = VIL
20
ns
tELLH
tELAVDH
Chip Enable Low to Latch
Enable High
E = VIL, G = VIH
10
ns
tELQV
(2)
tCE
Chip Enable Low to Output
Valid
G = VIL
100
120
ns
tELQX
(1)
tLZ
Chip Enable Low to Output
Transition
G = VIL
00
ns
tGHQX
tOH
Output Enable High to
Output Transition
E = VIL
00
ns
tGHQZ
(1)
tDF
Output Enable High to
Output Hi-Z
E = VIL
20
ns
tGLQV
(2)
tOE
Output Enable Low to
Output Valid
E = VIL
25
35
ns
tGLQX
(1)
tOLZ
Output Enable Low to
Output Transition
E = VIL
00
ns
tLHAX
tAVDHAX
Latch Enable High to
Address Transition
E = VIL, G = VIH
10
ns
tLHGL
Latch Enable High to
Output Enable Low
E = VIL
10
ns
tLLLH
tAVDLAVDH
Latch Enable Pulse Width
E = VIL, G = VIH
10
ns
tLLQV
tAVDLQV
Latch Enable Low to
Output Valid (Random)
E = VIL
100
120
ns
tLLQV1
Latch Enable Low to
Output Valid (Page)
E = VIL
45
ns
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