參數(shù)資料
型號(hào): M59MR032C100ZC6T
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 32兆位的2Mb x16插槽,復(fù)用的I / O,雙行,突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù): 11/49頁(yè)
文件大小: 352K
代理商: M59MR032C100ZC6T
19/49
M59MR032C, M59MR032D
Note: 1. Commands not interpreted in this table will default to read array mode.
2. For Coded cycles address inputs A11-A20 are don’t care.
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
mand cycles.
5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0.
7. High voltage on VPP (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.
BL
Block Lock
4
Addr.
555h
2AAh
555h
Block
Address
Data
AAh
55h
60h
2Fh
BE
Block Erase
6+
Addr.
555h
2AAh
555h
2AAh
Block
Address
Data
AAh
55h
80h
AAh
55h
30h
BKE
Bank Erase
6
Addr.
555h
2AAh
555h
2AAh
Bank
Address
Data
AAh
55h
80h
AAh
55h
10h
ES
Erase Suspend
1
Addr. (3)
X
Read until Toggle stops, then read all the data needed
from any Blocks not being erased then Resume Erase.
Data
B0h
ER
Erase Resume
1
Addr.
Bank
Address
Read Data Polling or Toggle Bits until Erase completes or
Erase is suspended another time
Data
30h
Mne.
Instr.
Cyc.
1st Cyc.
2nd Cyc.
3rd Cyc.
4th Cyc.
5th Cyc.
6th Cyc.
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