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參數(shù)資料
| 型號： | M485L1624FT0-LA2 |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | SODIMM-200 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 264K |
| 代理商： | M485L1624FT0-LA2 |
DDR SDRAM
128MB, 256MB SODIMM
Rev. 1.2 March 2004
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to Vss
VDDQ
-1.0 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.5 * # of component
W
Short circuit current
IOS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
Power & DC Operating Conditions (SSTL_2 In/Out)
Notes 1. Includes
± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of
≤ 3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70
°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
2.7
5
I/O Supply voltage
VDDQ
2.3
2.7
V
5
I/O Reference voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination voltage(system)
VTT
VREF-0.04
VREF+0.04
V
2
Input logic high voltage
VIH(DC)
VREF+0.15
VDDQ+0.3
V
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.36
VDDQ+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4
-
4
Input leakage current
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Normal strengh driver) ;VOUT =
VTT + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver) ;VOUT =
VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver) ;VOUT = VTT
+ 0.45V
IOH
-9
mA
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