參數(shù)資料
型號(hào)： M393B1K73CH0-YH9
元件分類： DRAM
英文描述： 1G X 72 MULTI DEVICE DRAM MODULE, 0.255 ns, DMA240
封裝： HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù)： 32/53頁(yè)
文件大?。?/td> 1492K
代理商： M393B1K73CH0-YH9
- 29 -
datasheet
DDR3L SDRAM
Rev. 1.01
Registered DIMM
[ Table 15 ] DDR3-1066 Speed Bins
[ Table 16 ] DDR3-1333 Speed Bins
Speed
DDR3-1066
Units
NOTE
CL-nRCD-nRP
7 - 7 - 7
Parameter
Symbol
min
max
Internal read command to first data
tAA
13.125
20
ns
ACT to internal read or write delay time
tRCD
13.125
-
ns
PRE command period
tRP
13.125
-
ns
ACT to ACT or REF command period
tRC
50.625
-
ns
ACT to PRE command period
tRAS
37.5
9*tREFI
ns
8
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,6
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 7
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
<2.5
ns
1,2,3,4
CL = 8
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
<2.5
ns
1,2,3
Supported CL Settings
6,7,8
nCK
Supported CWL Settings
5,6
nCK
Speed
DDR3-1333
Units
NOTE
CL-nRCD-nRP
9 -9 - 9
Parameter
Symbol
min
max
Internal read command to first data
tAA
13.5 (13.125)5,9
20
ns
ACT to internal read or write delay time
tRCD
13.5 (13.125)5,9
-
ns
PRE command period
tRP
13.5 (13.125)5,9
-
ns
ACT to ACT or REF command period
tRC
49.5 (49.125)5,9
-
ns
ACT to PRE command period
tRAS
36
9*tREFI
ns
8
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,7
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
Reserved
ns
4
CL = 7
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
<2.5
ns
1,2,3,4,7
(Optional) NOTE 5,9
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4,
CL = 8
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
<2.5
ns
1,2,3,7
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4,
CL = 9
CWL = 5,6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1,2,3,4
CL = 10
CWL = 5,6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1,2,3
(Optional)
ns
5
Supported CL Settings
6,7,8,9
nCK
Supported CWL Settings
5,6,7
nCK
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